BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Montreal BEGIN:DAYLIGHT DTSTART:20210314T030000 TZOFFSETFROM:-0500 TZOFFSETTO:-0400 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:EDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20211107T010000 TZOFFSETFROM:-0400 TZOFFSETTO:-0500 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:EST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20220110T151713Z UID:9980A2FB-F6CD-4021-B26B-85AB39C9A721 DTSTART;TZID=America/Montreal:20210317T110000 DTEND;TZID=America/Montreal:20210317T120000 DESCRIPTION:As the electronics industry is going through some rapid changes \, the new electronics systems need to provide increasingly higher perform ance. As a result\, the capability of the components that constitute these systems needs to also scale accordingly. One area where pace of innovatio n has greatly increased in recent years is semiconductor packaging. Paving the way for heterogeneous integration\, these new ‘advanced’ packagin g technologies aim to integrate multiple logic\, memory\, and other specia lized silicon dies\, potentially using different silicon process technolog ies\, and provide unprecedented levels of performance in metrics such as I O bandwidth\, bandwidth density\, and power efficiency. This presentation will review some of these new advanced packaging technologies such as fan- out wafer/panel level and 2.xD packaging and the key challenges and some s olutions for their electrical design and analysis.\n\nSpeaker(s): Dr. Kema l Aygun\, \n\nVirtual: https://events.vtools.ieee.org/m/266199 LOCATION:Virtual: https://events.vtools.ieee.org/m/266199 ORGANIZER:roni.khazaka@mcgill.ca SEQUENCE:1 SUMMARY:Trends and Challenges for Electrical Design and Analysis Using Adva nced Packaging URL;VALUE=URI:https://events.vtools.ieee.org/m/266199 X-ALT-DESC:Description: <br /><p>As the electronics industry is going throu gh some rapid changes\, the new electronics systems need to provide increa singly higher performance. As a result\, the capability of the components that constitute these systems needs to also scale accordingly. One area wh ere pace of innovation has greatly increased in recent years is semiconduc tor packaging. Paving the way for heterogeneous integration\, these new &l squo\;advanced&rsquo\; packaging technologies aim to integrate multiple lo gic\, memory\, and other specialized silicon dies\, potentially using diff erent silicon process technologies\, and provide unprecedented levels of p erformance in metrics such as IO bandwidth\, bandwidth density\, and power efficiency. This presentation will review some of these new advanced pack aging technologies such as fan-out wafer/panel level and 2.xD packaging an d the key challenges and some solutions for their electrical design and an alysis.</p> END:VEVENT END:VCALENDAR