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DTSTART:20210314T030000
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DTSTAMP:20210426T003252Z
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DTSTART;TZID=US/Pacific:20210422T170000
DTEND;TZID=US/Pacific:20210422T183000
DESCRIPTION:The following three practically important questions associated 
 with predicting and improving the reliability of solder joint interconnect
 ions (SJI) of IC packages are addressed in this seminar:\n\nI. Could inela
 stic strains in the solder material be avoided by a rational design\, and 
 if not\, could the sizes of the inelastic strain areas be predicted and \,
  if possible\, minimized?\n\nII. Considering that the difference between a
 n highly reliable and an insufficiently reliable product is “merely” i
 n the level of its never-zero probability of failure\, and that SJIs are u
 sually the most vulnerable structural elements in an IC package design\, c
 ould this probability be assessed at the design stage and\, if possible\, 
 made adequate for the given application?\n\nIII. Should temperature cyclin
 g accelerated testing for SJIs be replaced with a more physically meaningf
 ul\, less costly\, less time- and labor- consuming and\, most importantly\
 , less misleading accelerated test vehicle?\n\nSpeaker(s): Dr. Ephraim Suh
 ir\, \n\nSan Diego\, California\, United States\, Virtual: https://events.
 vtools.ieee.org/m/267150
LOCATION:San Diego\, California\, United States\, Virtual: https://events.v
 tools.ieee.org/m/267150
ORGANIZER:pthadesar@ieee.org
SEQUENCE:1
SUMMARY:IEEE EPS Webinar: Avoiding inelastic strains in solder joint interc
 onnections of IC packages
URL;VALUE=URI:https://events.vtools.ieee.org/m/267150
X-ALT-DESC:Description: <br /><p>The following three practically important 
 questions associated with predicting and improving the reliability of sold
 er joint interconnections (SJI) of IC packages are addressed in this semin
 ar:&nbsp\;</p>\n<p>I. Could inelastic strains in the solder material be av
 oided by a rational design\, and if not\, could the sizes of the inelastic
  strain areas be predicted and \, if possible\, minimized?&nbsp\;</p>\n<p>
 II. Considering that the difference between an highly reliable and an insu
 fficiently reliable product is &ldquo\;merely&rdquo\; in the level of its 
 never-zero probability of failure\, and that SJIs are usually the most vul
 nerable structural elements in an IC package design\, could this probabili
 ty be assessed at the design stage and\, if possible\, made adequate for t
 he given application?</p>\n<p>III. Should temperature cycling accelerated 
 testing for SJIs be replaced with a more physically meaningful\, less cost
 ly\, less time- and labor- consuming and\, most importantly\, less mislead
 ing accelerated test vehicle?</p>
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