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DESCRIPTION:Silicon interconnect fabric (Si-IF) promotes a paradigm shift i
 n ultra-large-scale heterogeneous integration. The Si-IF is a wafer-scale 
 platform that supports integration of heterogeneous bare (unpackaged) dies
 . The dies are connected using fine pitch vertical interconnects (pillars)
  designed directly on the Si-IF\, effectively eliminating the need for pac
 kage and printed circuit board. The pitch of the vertical pillars that are
  used to bond dies to the Si-IF is 2 to 10 μm\, and the minimal distance 
 between adjacent dies on the Si-IF is approximately 50 μm. The Si-IF supp
 orts SoC-like integration at a wafer level\, enabling scaled out applicati
 ons that were previously not practical (e.g.\, neuromorphic systems).\n\nT
 o enable the Si-IF as a practical platform for ultra-large-scale heterogen
 eous integration\, system-level design challenges must be addressed. Borro
 wing from a network-on-chip (NoC)\, a network on interconnect fabric (NoIF
 ) is proposed to support global communication on the Si-IF. Unlike NoCs\, 
 the NoIF is expected to provide additional system-level services\, includi
 ng power management\, synchronization\, and testing (built-in self-test) o
 n the Si-IF. The Si-IF is a passive platform\; utility dies (UDs) serve\, 
 therefore\, as intelligent nodes within the NoIF to support all of the ser
 vices that the network provides.\n\nCo-sponsored by: STARaCOM\n\nSpeaker(s
 ): Boris Vaisband\, PhD\, Assistant Prof.\, McGill University\, \n\nVirtua
 l: https://events.vtools.ieee.org/m/267793
LOCATION:Virtual: https://events.vtools.ieee.org/m/267793
ORGANIZER:roni.khazaka@mcgill.ca
SEQUENCE:4
SUMMARY:Wafer-Scale Heterogeneous Integration
URL;VALUE=URI:https://events.vtools.ieee.org/m/267793
X-ALT-DESC:Description: <br /><p>Silicon interconnect fabric (Si-IF) promot
 es a paradigm shift in ultra-large-scale heterogeneous integration. The Si
 -IF is a wafer-scale platform that supports integration of heterogeneous b
 are (unpackaged) dies. The dies are connected using fine pitch vertical in
 terconnects (pillars) designed directly on the Si-IF\, effectively elimina
 ting the need for package and printed circuit board. The pitch of the vert
 ical pillars that are used to bond dies to the Si-IF is 2 to 10 &mu\;m\, a
 nd the minimal distance between adjacent dies on the Si-IF is approximatel
 y 50 &mu\;m. The Si-IF supports SoC-like integration at a wafer level\, en
 abling scaled out applications that were previously not practical (<em>e.g
 .</em>\, neuromorphic systems).</p>\n<p>&nbsp\;</p>\n<p>To enable the Si-I
 F as a practical platform for ultra-large-scale heterogeneous integration\
 , system-level design challenges must be addressed. Borrowing from a netwo
 rk-on-chip (NoC)\, a network on interconnect fabric (NoIF) is proposed to 
 support global communication on the Si-IF. Unlike NoCs\, the NoIF is expec
 ted to provide additional system-level services\, including power manageme
 nt\, synchronization\, and testing (built-in self-test) on the Si-IF. The 
 Si-IF is a passive platform\; utility dies (UDs) serve\, therefore\, as in
 telligent nodes within the NoIF to support all of the services that the ne
 twork provides.</p>
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