BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Canada/Eastern BEGIN:DAYLIGHT DTSTART:20210314T030000 TZOFFSETFROM:-0500 TZOFFSETTO:-0400 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:EDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20211107T010000 TZOFFSETFROM:-0400 TZOFFSETTO:-0500 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:EST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20211108T135858Z UID:25E37507-1CAC-49EE-829D-05F4A8B89538 DTSTART;TZID=Canada/Eastern:20210413T150000 DTEND;TZID=Canada/Eastern:20210413T160000 DESCRIPTION:Monolithic ICs have progressed at an unprecedented rate of inno vation in the past ~60 years. But\, with Moore’s Law slowing down\, ‘p olylithic' integration of heterogeneous ICs and devices is projected to be a key driver for performance\, power\, and cost in the next phase of Moor e’s Law.\n\nThis presentation will first discuss various emerging hetero geneous integration approaches using 2.5D and 3D IC technologies\, includi ng those being developed at Georgia Tech’s Integrated 3D Systems Lab. De sign considerations and benchmarking of power delivery\, signaling\, and t hermal are also described. Second\, a passive self-alignment and assembly approach for optical fibers is demonstrated using a combination of silicon micromachining and 3D printing to achieve sub-micron alignment accuracy t o underlying silicon-on-insulator (SOI) substrate with monolithic waveguid es and couplers in 2.5D/3D IC platforms.\n\nThird\, there exists a perform ance gap between TSV-based 3D and monolithic 3D ICs in terms of energy\, b andwidth\, and interconnect density. To bridge this gap\, a 3D polylithic integration scheme is proposed which represents a densely integrated syste m divided into multiple heterogeneously integrated device tiers. This sche me\, termed 3D seamless off-chip connectivity (3D SoC+)\, aims to combine the best of monolithic and TSV-based 3D ICs\, including extreme efficient signaling and massive interconnect density without the fabrication limits of monolithic 3D ICs. As an enabling technology for 3D SoC+\, we demonstra te the feasibility of using selective thermal cobalt ALD for Cu-Cu interco nnect bonding at low temperature (200 oC).\n\nLastly\, we experimentally d emonstrate embedded microfluidic cooling technologies for 2.5D/3D IC archi tectures with electrical via integration to enable dense 2.5D/3D electroni cs with no thermal limits.\n\nSpeaker(s): Prof. Muhannad Bakir\, \n\nVirtu al: https://events.vtools.ieee.org/m/268786 LOCATION:Virtual: https://events.vtools.ieee.org/m/268786 ORGANIZER:m4asad@uwaterloo.ca SEQUENCE:1 SUMMARY:Emerging 2.5D and 3D Heterogeneous Integration Architectures for th e Next Phase of Moore’s Law URL;VALUE=URI:https://events.vtools.ieee.org/m/268786 X-ALT-DESC:Description: <br /><div class="" data-block="true" data-editor=" ct1rv" data-offset-key="e6f9c-0-0">\n<div class="public-DraftStyleDefault- block public-DraftStyleDefault-ltr" data-offset-key="e6f9c-0-0"><span data -offset-key="e6f9c-0-1">Monolithic ICs have progressed at an unprecedented rate of innovation in the past ~60 years. But\, with Moore&rsquo\;s Law s lowing down\, &lsquo\;polylithic' integration of heterogeneous ICs and dev ices is projected to be a key driver for performance\, power\, and cost in the next phase of Moore&rsquo\;s Law.</span></div>\n</div>\n<div class="" data-block="true" data-editor="ct1rv" data-offset-key="e6tcj-0-0">\n<div class="public-DraftStyleDefault-block public-DraftStyleDefault-ltr" data-o ffset-key="e6tcj-0-0"><span data-offset-key="e6tcj-0-0">This presentation will first discuss various emerging heterogeneous integration approaches u sing 2.5D and 3D IC technologies\, including those being developed at Geor gia Tech&rsquo\;s Integrated 3D Systems Lab. Design considerations and ben chmarking of power delivery\, signaling\, and thermal are also described. Second\, a passive self-alignment and assembly approach for optical fibers is demonstrated using a combination of silicon micromachining and 3D prin ting to achieve sub-micron alignment accuracy to underlying silicon-on-ins ulator (SOI) substrate with monolithic waveguides and couplers in 2.5D/3D IC platforms.</span></div>\n</div>\n<div class="" data-block="true" data-e ditor="ct1rv" data-offset-key="4f058-0-0">\n<div class="public-DraftStyleD efault-block public-DraftStyleDefault-ltr" data-offset-key="4f058-0-0"><sp an data-offset-key="4f058-0-0">Third\, there exists a performance gap betw een TSV-based 3D and monolithic 3D ICs in terms of energy\, bandwidth\, an d interconnect density. To bridge this gap\, a 3D polylithic integration s cheme is proposed which represents a densely integrated system divided int o multiple heterogeneously integrated device tiers. This scheme\, termed 3 D seamless off-chip connectivity (3D SoC+)\, aims to combine the best of m onolithic and TSV-based 3D ICs\, including extreme efficient signaling and massive interconnect density without the fabrication limits of monolithic 3D ICs. As an enabling technology for 3D SoC+\, we demonstrate the feasib ility of using selective thermal cobalt ALD for Cu-Cu interconnect bonding at low temperature (200 oC).</span></div>\n</div>\n<div class="" data-blo ck="true" data-editor="ct1rv" data-offset-key="fbjoi-0-0">\n<div class="pu blic-DraftStyleDefault-block public-DraftStyleDefault-ltr" data-offset-key ="fbjoi-0-0"><span data-offset-key="fbjoi-0-0">Lastly\, we experimentally demonstrate embedded microfluidic cooling technologies for 2.5D/3D IC arch itectures with electrical via integration to enable dense 2.5D/3D electron ics with no thermal limits.</span></div>\n</div> END:VEVENT END:VCALENDAR