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DTSTART:20210314T030000
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DTSTART:20211107T010000
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DTSTAMP:20220316T014821Z
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DTSTART;TZID=America/Los_Angeles:20210506T110000
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DESCRIPTION:Several factors drive the demand for DRAM bandwidth scaling: in
  addition to established applications in visualization\, there has been a 
 proliferation of data-intensive applications enabled by advancements in AI
 \, ML and advanced driver-assistance systems (ADAS) [1]. While high-bandwi
 dth memory (HBM) provides an alternative solution\, its high cost makes it
  impractical for many applications. On the other hand\, extending the GDDR
  roadmap beyond GDDR6 through per-pin bandwidth scaling presents significa
 nt obstacles: including the reduced link-timing budget and the slow DRAM t
 ransistors. This paper introduces an 8Gb DRAM with a single-ended PAM4 int
 erface to redirect and extend the GDDR roadmap. The design supports 22Gb/s
 /pin in a conventional 1Ynm DRAM process.\n\nSpeaker(s): Dr. Timothy M. Ho
 llis \, \n\nSan Diego\, California\, United States\, Virtual: https://even
 ts.vtools.ieee.org/m/270177
LOCATION:San Diego\, California\, United States\, Virtual: https://events.v
 tools.ieee.org/m/270177
ORGANIZER:jfshi@ieee.org
SEQUENCE:1
SUMMARY:An 8 Gb GDDR6X DRAM Achieving 22 Gb/s/pin with Single-ended PAM-4 S
 ignaling
URL;VALUE=URI:https://events.vtools.ieee.org/m/270177
X-ALT-DESC:Description: <br /><p>Several factors drive the demand for DRAM 
 bandwidth scaling: in addition to established applications in visualizatio
 n\, there has been a proliferation of data-intensive applications enabled 
 by advancements in AI\, ML and advanced driver-assistance systems (ADAS) [
 1]. While high-bandwidth memory (HBM) provides an alternative solution\, i
 ts high cost makes it impractical for many applications. On the other hand
 \, extending the GDDR roadmap beyond GDDR6 through per-pin bandwidth scali
 ng presents significant obstacles: including the reduced link-timing budge
 t and the slow DRAM transistors. This paper introduces an 8Gb DRAM with a 
 single-ended PAM4 interface to redirect and extend the GDDR roadmap. The d
 esign supports 22Gb/s/pin in a conventional 1Ynm DRAM process.</p>
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