BEGIN:VCALENDAR
VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:America/Santiago
BEGIN:DAYLIGHT
DTSTART:20210905T010000
TZOFFSETFROM:-0400
TZOFFSETTO:-0300
RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=9
TZNAME:-03
END:DAYLIGHT
BEGIN:STANDARD
DTSTART:20210403T230000
TZOFFSETFROM:-0300
TZOFFSETTO:-0400
RRULE:FREQ=YEARLY;BYDAY=1SA;BYMONTH=4
TZNAME:-04
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20210604T133043Z
UID:92377AC8-D98D-4A2D-A33C-A033106D99A4
DTSTART;TZID=America/Santiago:20210603T120000
DTEND;TZID=America/Santiago:20210603T130000
DESCRIPTION:In this presentation we argue and provide Non-Equilibrium Green
 ’s Function Landauer formalism-based simulation evidence that in spite o
 f Graphene’s bandgap absence\, Graphene Nanoribbons (GNRs) can provide s
 upport for energy effective computing. We start by demonstrating that: (i)
  band gap can be opened by means of GNR topology and (ii) GNR’s conducta
 nce can be mold according to some desired functionality\, i.e.\, 2- and 3-
 input AND\, NAND\, OR\, NOR\, XOR\, and XNOR\, via shape and electrostatic
  interaction. Afterwards\, we introduce a generic GNR based Boolean gate s
 tructure composed of a pull-up GNR performing the gate Boolean function an
 d a pull-down GNR performing the gate inverted Boolean function\, and\, by
  properly adjusting GNRs' dimensions and topology\, we design and evaluate
  by means of SPICE simulations inverter\, buffer\, and 2-input GNR based A
 ND\, NAND\, and XOR gates. When compared with state-of-the-art graphene FE
 T and CMOS based counterparts the GNR-based gates outperform its challenge
 rs\, e.g.\, up to 6x smaller propagation delay\, 2 orders of magnitude sma
 ller power consumption\, while requiring 1 to 2 orders of magnitude smalle
 r active area footprint than 7nm CMOS equivalents. Finally\, to get better
  inside in the practical implications of the proposed approach\, we presen
 t Full Adder (FA) and SRAM cell GNR designs\, as they are currently fundam
 ental components for the construction of any computation system. For an ef
 fective FA implementation\, we introduce a 3-input MAJORITY gate\, which a
 part of being able to directly compute FA's carry-out is an essential elem
 ent in the implementation of Error Correcting Codes codecs\, that outperfo
 rms a 7nm CMOS equivalent Carry-Out calculation circuit by 2 and 3 orders 
 of magnitude in terms of delay and power consumption\, respectively\, whil
 e requiring 2 orders of magnitude less area. The proposed FA exhibits 6x s
 maller delay\, 3 orders of magnitude less power consumption\, while requir
 ing 2 orders of magnitude less area than a 7 nm FinFET CMOS counterpart. H
 owever\, because of the effective carry-out circuitry\, a GNR-based n-bit 
 Ripple Carry Adder\, whose performance is linear in the Carry-Out path del
 ay\, will be 108x faster than an equivalent CMOS implementation. The GNR-b
 ased SRAM cell provides a slightly better resilience to DC-noise character
 istics\, while performance-wise has a 3x smaller delay\, consumes 2 orders
  of magnitude less power\, and requires 1 order of magnitude less area tha
 n the CMOS equivalent. These results clearly indicate that the proposed GN
 R-based approach is opening a promising avenue towards future competitive 
 carbon-based nanoelectronics.\n\nCo-sponsored by: Synopsys\n\nSpeaker(s): 
 Sorin Cotofana\, \n\nSantiago\, Region Metropolitana\, Chile\, Virtual: ht
 tps://events.vtools.ieee.org/m/272315
LOCATION:Santiago\, Region Metropolitana\, Chile\, Virtual: https://events.
 vtools.ieee.org/m/272315
ORGANIZER:victor.grimblatt@synopsys.com
SEQUENCE:1
SUMMARY:Energy Effective Graphene Based Computing
URL;VALUE=URI:https://events.vtools.ieee.org/m/272315
X-ALT-DESC:Description: <br /><p>In this presentation we argue and provide 
 Non-Equilibrium Green&rsquo\;s Function Landauer formalism-based simulatio
 n evidence that in spite of Graphene&rsquo\;s bandgap&nbsp\;absence\, Grap
 hene Nanoribbons (GNRs) can provide support for energy effective computing
 .&nbsp\; We start by demonstrating that: (i) band gap can be opened by&nbs
 p\;means of GNR topology and (ii) GNR&rsquo\;s conductance can be mold acc
 ording to some desired functionality\, i.e.\, 2- and 3-input AND\, NAND\, 
 OR\, NOR\, XOR\, and XNOR\, via shape and electrostatic interaction. After
 wards\, we introduce&nbsp\;a generic GNR based Boolean gate structure comp
 osed of a pull-up GNR performing the gate Boolean function and a pull-down
  GNR performing the gate&nbsp\;inverted Boolean function\, and\, by proper
 ly adjusting GNRs' dimensions and topology\, we design and evaluate by mea
 ns of SPICE simulations inverter\, buffer\, and 2-input GNR based AND\, NA
 ND\,&nbsp\;and XOR gates. When compared with state-of-the-art graphene FET
  and CMOS based counterparts the GNR-based gates outperform its challenger
 s\, e.g.\, up to 6x smaller propagation delay\, 2 orders of magnitude smal
 ler power consumption\, while requiring 1 to 2 orders of&nbsp\;magnitude s
 maller active area footprint than 7nm CMOS equivalents. Finally\, to get b
 etter inside in the practical implications of the proposed approach\, we p
 resent Full Adder (FA) and SRAM cell GNR designs\, as they are currently f
 undamental components for the construction of any computation system. For 
 an effective FA implementation\, we introduce a 3-input MAJORITY gate\, wh
 ich apart of being able to directly compute FA's carry-out is an essential
  element in the implementation of Error Correcting Codes codecs\, that out
 performs a 7nm CMOS equivalent Carry-Out calculation circuit by 2 and 3 or
 ders of magnitude in terms of delay and power consumption\, respectively\,
  while requiring 2 orders of magnitude less area. The proposed FA exhibits
  6x smaller delay\, 3 orders of magnitude less power consumption\, while r
 equiring 2 orders of magnitude less area than a 7 nm FinFET CMOS counterpa
 rt. However\, because of the effective carry-out circuitry\, a GNR-based n
 -bit Ripple Carry Adder\, whose performance is linear in the Carry-Out pat
 h delay\, will be 108x faster than an equivalent CMOS implementation. The 
 GNR-based SRAM cell provides a slightly better resilience to DC-noise char
 acteristics\, while performance-wise has a 3x smaller delay\, consumes 2 o
 rders of magnitude less power\, and requires 1 order of magnitude less are
 a than the CMOS equivalent. These results clearly indicate that the propos
 ed GNR-based approach is opening a promising avenue towards future competi
 tive carbon-based nanoelectronics.&nbsp\;</p>
END:VEVENT
END:VCALENDAR