BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Los_Angeles BEGIN:DAYLIGHT DTSTART:20210314T030000 TZOFFSETFROM:-0800 TZOFFSETTO:-0700 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:PDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20211107T010000 TZOFFSETFROM:-0700 TZOFFSETTO:-0800 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:PST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20210604T231553Z UID:7462DCC9-59E9-4AE6-8177-12259FB19C83 DTSTART;TZID=America/Los_Angeles:20210604T090000 DTEND;TZID=America/Los_Angeles:20210604T103000 DESCRIPTION:Semiconductor demand is rapidly expanding beyond the computing and mobile markets with more products being introduced for automotive\, in dustrial\, medical\, avionics\, and space applications. Chips are increasi ngly complex with growing functionality through integration of more digita l\, analog/mixed-signal\, and RF sub-systems. Technologies still continue to scale to ever-shrinking dimensions with novel materials and device arch itectures to realize new power-performance-area levels. Although these new capabilities enable diversified product opportunities\, guaranteeing reli ability and quality over long product lifetimes has become increasingly ch allenging in such applications. This paper provides an overview of reliabi lity and product quality challenges in advanced CMOS nodes comprising finF ET and fully depleted silicon-on-insulator technologies. Following an over view of intrinsic and extrinsic reliability mechanisms along with design a nd test methodologies for improving reliability and product quality\, it a ddresses key reliability challenges in fully depleted technologies\, such as self-heating\, I/O scaling\, middle-of-line reliability\, dielectric-br eakdown monitoring\, variation\, and stochastic aging. To meet these more stringent requirements in advanced technologies\, chip designers and manuf acturers must collaboratively optimize chip process technology\, design\, and test in an even more cohesive and transparent partnership.\n\nSpeaker( s): Mehul Shroff\, \n\nSan Diego\, California\, United States\, Virtual: h ttps://events.vtools.ieee.org/m/273084 LOCATION:San Diego\, California\, United States\, Virtual: https://events.v tools.ieee.org/m/273084 ORGANIZER:jfshi@ieee.org SEQUENCE:1 SUMMARY:Design-Technology Co-Optimization for Reliability and Quality in Ad vanced Nodes URL;VALUE=URI:https://events.vtools.ieee.org/m/273084 X-ALT-DESC:Description: <br /><p>Semiconductor demand is rapidly expanding beyond the computing and mobile markets with more products being introduce d for automotive\, industrial\, medical\, avionics\, and space application s. Chips are increasingly complex with growing functionality through integ ration of more digital\, analog/mixed-signal\, and RF sub-systems. Technol ogies still continue to scale to ever-shrinking dimensions with novel mate rials and device architectures to realize new power-performance-area level s. Although these new capabilities enable diversified product opportunitie s\, guaranteeing reliability and quality over long product lifetimes has b ecome increasingly challenging in such applications. This paper provides a n overview of reliability and product quality challenges in advanced CMOS nodes comprising finFET and fully depleted silicon-on-insulator technologi es. Following an overview of intrinsic and extrinsic reliability mechanism s along with design and test methodologies for improving reliability and p roduct quality\, it addresses key reliability challenges in fully depleted technologies\, such as self-heating\, I/O scaling\, middle-of-line reliab ility\, dielectric-breakdown monitoring\, variation\, and stochastic aging . To meet these more stringent requirements in advanced technologies\, chi p designers and manufacturers must collaboratively optimize chip process t echnology\, design\, and test in an even more cohesive and transparent par tnership.</p> END:VEVENT END:VCALENDAR