BEGIN:VCALENDAR
VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:Asia/Kolkata
BEGIN:STANDARD
DTSTART:19451014T230000
TZOFFSETFROM:+0630
TZOFFSETTO:+0530
TZNAME:IST
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20210626T045136Z
UID:51BF42E2-17C9-42ED-A020-74E28BC6F872
DTSTART;TZID=Asia/Kolkata:20210614T183000
DTEND;TZID=Asia/Kolkata:20210618T200000
DESCRIPTION:This Workshop addresses Advance Digital Design\, CMOS\, Introdu
 ction to Verilog\, System Verilog and UVM and address the growing semicond
 uctor industry landscape\, trends\, opportunities\, skills needed to join 
 the VLSI/Semiconductor Industry and bridge the gap between academics and s
 emiconductor industry requirements\n\nBangalore\, Karnataka\, India\, Virt
 ual: https://events.vtools.ieee.org/m/273566
LOCATION:Bangalore\, Karnataka\, India\, Virtual: https://events.vtools.iee
 e.org/m/273566
ORGANIZER:jalajas@ieee.org
SEQUENCE:3
SUMMARY:One-Week Continuing Education Programme workshop On RTL Design and 
 Verification
URL;VALUE=URI:https://events.vtools.ieee.org/m/273566
X-ALT-DESC:Description: <br /><p>This Workshop addresses Advance Digital De
 sign\, CMOS\, Introduction to Verilog\, System Verilog and UVM and address
  the growing semiconductor industry landscape\, trends\, opportunities\, s
 kills needed to join the VLSI/Semiconductor Industry and bridge the gap be
 tween academics and semiconductor industry requirements</p>
END:VEVENT
END:VCALENDAR