BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Europe/Warsaw BEGIN:DAYLIGHT DTSTART:20210328T030000 TZOFFSETFROM:+0100 TZOFFSETTO:+0200 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=3 TZNAME:CEST END:DAYLIGHT BEGIN:STANDARD DTSTART:20211031T020000 TZOFFSETFROM:+0200 TZOFFSETTO:+0100 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=10 TZNAME:CET END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20220114T094724Z UID:C8D7CD08-D0D6-47B1-B16D-122BB8BA5D44 DTSTART;TZID=Europe/Warsaw:20210629T143000 DTEND;TZID=Europe/Warsaw:20210629T160000 DESCRIPTION:Abstract: Modern SoCs for advanced applications are integrating an increasing number of phase-locked loops (PLLs) into a single silicon d ie. 5G transceivers require multiple PLLs to implement complex schemes of carrier aggregation and MIMO. Multi-core processors also have to use many PLLs to generate independent clock frequencies for each core to operate at the optimum performance. With this trend\, an area-efficient design of PL Ls becomes more important. In this point of view\, i.e.\, the efficiency i n the use of silicon\, ring-oscillator-based digital PLLs (DPLLs) have obv ious merits over conventional LC VCO-based charge-pump PLLs. Ring-oscillat or-based DPLLs also have an advantage in terms of the scalability with new CMOS technologies. They also can be implemented in some CMOS technologies where high-quality metal layers for inductors are not available. Despite foregoing merits\, their poor jitter performance has limited their popular ity in high-performance applications that generally require a clock signal having an ultra-low jitter. This lecture introduces recent architectures of low-jitter ring-oscillator-based DPLLs and presents key enabling circui t techniques to resolve their problems\, such as thermal and flicker noise s of ring oscillators\, reference spurs\, and fractional spurs. Finally\, we discuss the limit of ring-oscillator-based DPLLs and the possibility of their adaptation to high-performance applications.\n\nSpeaker's Bio:\n\nJ aehyouk Choi (S’06–M’11) was born in Seoul\, South Korea. He receive d the B.S. degree (summa cum laude) in electrical engineering from Seoul N ational University\, Seoul\, South Korea\, in 2003\, and the M.S. and Ph.D . degrees in electrical and computer engineering from Georgia Institute of Technology\, Atlanta\, GA\, USA\, in 2008 and 2010\, respectively.\n\nFro m 2010 to 2011\, he was with Qualcomm\, Inc.\, San Diego\, CA\, USA\, wher e he was involved in designing multi-standard cellular transceivers. In 20 12\, he joined the Ulsan National Institute of Science and Technology (UNI ST)\, Ulsan\, South Korea\, and served as a faculty member. Since 2019\, h e has been an Associate Professor at the Korea Advanced Institute of Scien ce and Technology (KAIST)\, Daejeon\, South Korea.\n\nDr. Choi has been a TPC member of the IEEE ISSCC since 2017 and the IEEE ESSCIRC since 2016. H e was the country representative of Korea for the ISSCC Far-East region in 2018. He have authored and coauthored more than 60 journal and conference publications. His research interests include low-power and high-performan ce analog\, mixed signal\, and RF integrated circuits for emerging wireles s/wired communication standards.\n\nVirtual: https://events.vtools.ieee.or g/m/273657 LOCATION:Virtual: https://events.vtools.ieee.org/m/273657 ORGANIZER:kasinski@agh.edu.pl SEQUENCE:4 SUMMARY:Low-jitter ring-oscillator-based digital PLLs URL;VALUE=URI:https://events.vtools.ieee.org/m/273657 X-ALT-DESC:Description: <br /><p><strong>Abstract: </strong>Modern SoCs for advanced applications are integrating an increasing number of phase-locke d loops (PLLs) into a single silicon die. 5G transceivers require multiple PLLs to implement complex schemes of carrier aggregation and MIMO. Multi- core processors also have to use many PLLs to generate independent clock f requencies for each core to operate at the optimum performance. With this trend\, an area-efficient design of PLLs becomes more important. In this p oint of view\, i.e.\, the efficiency in the use of silicon\, ring-oscillat or-based digital PLLs (DPLLs) have obvious merits over conventional LC VCO -based charge-pump PLLs. Ring-oscillator-based DPLLs also have an advantag e in terms of the scalability with new CMOS technologies. They also can be implemented in some CMOS technologies where high-quality metal layers for inductors are not available. Despite foregoing merits\, their poor jitter performance has limited their popularity in high-performance applications that generally require a clock signal having an ultra-low jitter. This le cture introduces recent architectures of low-jitter ring-oscillator-based DPLLs and presents key enabling circuit techniques to resolve their proble ms\, such as thermal and flicker noises of ring oscillators\, reference sp urs\, and fractional spurs. Finally\, we discuss the limit of ring-oscilla tor-based DPLLs and the possibility of their adaptation to high-performanc e applications.</p>\n<p style="font-weight: 400\;"><strong>Speaker's Bio:< /strong></p>\n<p style="font-weight: 400\;">Jaehyouk Choi (S&rsquo\;06&nda sh\;M&rsquo\;11) was born in Seoul\, South Korea. He received the B.S. deg ree (summa cum laude) in electrical engineering from Seoul National Univer sity\, Seoul\, South Korea\, in 2003\, and the M.S. and Ph.D. degrees in e lectrical and computer engineering from Georgia Institute of Technology\, Atlanta\, GA\, USA\, in 2008 and 2010\, respectively.</p>\n<p style="font- weight: 400\;">From 2010 to 2011\, he was with Qualcomm\, Inc.\, San Diego \, CA\, USA\, where he was involved in designing multi-standard cellular t ransceivers. In 2012\, he joined the Ulsan National Institute of Science a nd Technology (UNIST)\, Ulsan\, South Korea\, and served as a faculty memb er. Since 2019\, he has been an Associate Professor at the Korea Advanced Institute of Science and Technology (KAIST)\, Daejeon\, South Korea.</p>\n <p style="font-weight: 400\;">Dr. Choi has been a TPC member of the IEEE I SSCC since 2017 and the IEEE ESSCIRC since 2016. He was the country repres entative of Korea for the ISSCC Far-East region in 2018. He have authored and coauthored more than 60 journal and conference publications. His resea rch interests include low-power and high-performance analog\, mixed signal \, and RF integrated circuits for emerging wireless/wired communication st andards.</p>\n<p>&nbsp\;</p> END:VEVENT END:VCALENDAR