BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Europe/Warsaw BEGIN:DAYLIGHT DTSTART:20210328T030000 TZOFFSETFROM:+0100 TZOFFSETTO:+0200 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=3 TZNAME:CEST END:DAYLIGHT BEGIN:STANDARD DTSTART:20211031T020000 TZOFFSETFROM:+0200 TZOFFSETTO:+0100 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=10 TZNAME:CET END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20220114T095041Z UID:C2FDBAAC-16E9-4709-88EB-D3877C83C59F DTSTART;TZID=Europe/Warsaw:20210624T143000 DTEND;TZID=Europe/Warsaw:20210624T160000 DESCRIPTION:Abstract:\n\nNoise coupling in RF system-on-chip integration is studied by on-chip and on-board measurements as well as by concatenated s imulations at chip and system levels. Integrated power and substrate noise simulation techniques use chip-package-system board combined circuit mode ls and verify noise coupling in mixed analog-digital integration. Wireless system level simulation evaluates the impacts of coupled RF noises on wir eless performance through metrics of throughput and error vector magnitude (EVM). In addition\, post-silicon techniques at packaging and assembly st ages are potential options to mitigate RF noise coupling problems. The pre sentation will also include demonstrations with test vehicles.\n\nSpeaker' s Bio:\n\nMakoto Nagata received the B.S. and M.S. degrees in physics from Gakushuin University\, Tokyo\, in 1991 and 1993\, respectively\, and a Ph .D. in electronics engineering from Hiroshima University\, Hiroshima\, in 2001. He was a research associate at Hiroshima University from 1994 to 200 2\, an associate professor at Kobe University from 2002 to 2009 and promot ed to a full professor in 2009. He is currently a professor of the graduat e school of science\, technology and innovation\, Kobe University\, Kobe\, Japan. He is a senior member of IEICE and IEEE.\n\nHis research interests include design techniques targeting high-performance mixed analog\, RF an d digital VLSI systems with particular emphasis on power/signal/substrate integrity and electromagnetic compatibility\, testing and diagnosis\, thre e-dimensional system integration\, as well as their applications for hardw are security and safety.\n\nDr. Nagata has been a member of a variety of t echnical program committees of international conferences such as the Sympo sium on VLSI Circuits (2002-2009)\, Custom Integrated Circuits Conference (2007-2009)\, Asian Solid-State Circuits Conference (2005-2009)\, Internat ional Solid-State Circuits Conference (2014-2017)\, European Solid-State C ircuits Conference (2020-) and many others. He is chairing the Technology Directions subcommittee for International Solid-State Circuits Conference (2018-present). He is also serving as SSCS AdCom member (2020-). He is cur rently an associate editor for IEEE Transactions on VLSI Systems (2015-pre sent). He was a technical program chair (2010-2011)\, a symposium chair (2 012-2013) and an executive committee member (2014-2015) for the Symposium on VLSI circuits\, and also a chair for IEEE SSCS\n\nVirtual: https://even ts.vtools.ieee.org/m/273658 LOCATION:Virtual: https://events.vtools.ieee.org/m/273658 ORGANIZER:kasinski@agh.edu.pl SEQUENCE:2 SUMMARY:Understanding\, Mitigation\, and Impacts on Wireless Communication Performance URL;VALUE=URI:https://events.vtools.ieee.org/m/273658 X-ALT-DESC:Description: <br /><p><strong>Abstract:</strong></p>\n<p>Noise c oupling in RF system-on-chip integration is studied by on-chip and on-boar d measurements as well as by concatenated simulations at chip and system l evels. Integrated power and substrate noise simulation techniques use chip -package-system board combined circuit models and verify noise coupling in mixed analog-digital integration. Wireless system level simulation evalua tes the impacts of coupled RF noises on wireless performance through metri cs of throughput and error vector magnitude (EVM). In addition\, post-sili con techniques at packaging and assembly stages are potential options to m itigate RF noise coupling problems. The presentation will also include dem onstrations with test vehicles.</p>\n<p><strong>Speaker's Bio:</strong></p >\n<p style="font-weight: 400\;">Makoto Nagata received the B.S. and M.S. degrees in physics from Gakushuin University\, Tokyo\, in 1991 and 1993\, respectively\, and a Ph.D. in electronics engineering from Hiroshima Unive rsity\, Hiroshima\, in 2001. He was a research associate at Hiroshima Univ ersity from 1994 to 2002\, an associate professor at Kobe University from 2002 to 2009 and promoted to a full professor in 2009. He is currently a p rofessor of the graduate school of science\, technology and innovation\, K obe University\, Kobe\, Japan. He is a senior member of IEICE and IEEE.</p >\n<p style="font-weight: 400\;">His research interests include design tec hniques targeting high-performance mixed analog\, RF and digital VLSI syst ems with particular emphasis on power/signal/substrate integrity and elect romagnetic compatibility\, testing and diagnosis\, three-dimensional syste m integration\, as well as their applications for hardware security and sa fety.</p>\n<p style="font-weight: 400\;">Dr. Nagata has been a member of a variety of technical program committees of international conferences such as the Symposium on VLSI Circuits (2002-2009)\, Custom Integrated Circuit s Conference (2007-2009)\, Asian Solid-State Circuits Conference (2005-200 9)\, International Solid-State Circuits Conference (2014-2017)\, European Solid-State Circuits Conference (2020-) and many others. He is chairing th e Technology Directions subcommittee for International Solid-State Circuit s Conference (2018-present). He is also serving as SSCS AdCom member (2020 -). He is currently an associate editor for IEEE Transactions on VLSI Syst ems (2015-present). He was a technical program chair (2010-2011)\, a sympo sium chair (2012-2013) and an executive committee member (2014-2015) for t he Symposium on VLSI circuits\, and also a chair for IEEE SSCS</p> END:VEVENT END:VCALENDAR