BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Europe/Warsaw BEGIN:DAYLIGHT DTSTART:20210328T030000 TZOFFSETFROM:+0100 TZOFFSETTO:+0200 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=3 TZNAME:CEST END:DAYLIGHT BEGIN:STANDARD DTSTART:20211031T020000 TZOFFSETFROM:+0200 TZOFFSETTO:+0100 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=10 TZNAME:CET END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20220114T094646Z UID:03201D70-14C9-4293-BE1C-1A4881F5A705 DTSTART;TZID=Europe/Warsaw:20210615T143000 DTEND;TZID=Europe/Warsaw:20210615T160000 DESCRIPTION:Abstract:\n\nInteractions of IC chips and packaging structures differentiate the electronic performance of power delivery networks (PDNs) in traditional 2D and advanced 2.5D and 3D technologies. This presentatio n discusses their impacts on signal integrity (SI)\, power integrity (PI)\ , electromagnetic compatibility (EMC) and electrostatic discharge protecti on (ESD)\, through in-depth Si experiments with in-place noise measurement s and full-chip level noise simulations. Test vehicles under study are giv en in traditional 2D face up and flip chip packaging\, 2.5D fan-out wafer level packaging (FOWLP)\, and 3D chip stacking with through silicon vias ( TSVs).\n\nSpeaker's Bio:\n\nMakoto Nagata received the B.S. and M.S. degre es in physics from Gakushuin University\, Tokyo\, in 1991 and 1993\, respe ctively\, and a Ph.D. in electronics engineering from Hiroshima University \, Hiroshima\, in 2001. He was a research associate at Hiroshima Universit y from 1994 to 2002\, an associate professor at Kobe University from 2002 to 2009 and promoted to a full professor in 2009. He is currently a profes sor of the graduate school of science\, technology and innovation\, Kobe U niversity\, Kobe\, Japan. He is a senior member of IEICE and IEEE.\n\nHis research interests include design techniques targeting high-performance mi xed analog\, RF and digital VLSI systems with particular emphasis on power /signal/substrate integrity and electromagnetic compatibility\, testing an d diagnosis\, three-dimensional system integration\, as well as their appl ications for hardware security and safety.\n\nDr. Nagata has been a member of a variety of technical program committees of international conferences such as the Symposium on VLSI Circuits (2002-2009)\, Custom Integrated Ci rcuits Conference (2007-2009)\, Asian Solid-State Circuits Conference (200 5-2009)\, International Solid-State Circuits Conference (2014-2017)\, Euro pean Solid-State Circuits Conference (2020-) and many others. He is chairi ng the Technology Directions subcommittee for International Solid-State Ci rcuits Conference (2018-present). He is also serving as SSCS AdCom member (2020-). He is currently an associate editor for IEEE Transactions on VLSI Systems (2015-present). He was a technical program chair (2010-2011)\, a symposium chair (2012-2013) and an executive committee member (2014-2015) for the Symposium on VLSI circuits\, and also a chair for IEEE SSCS\n\nVir tual: https://events.vtools.ieee.org/m/273659 LOCATION:Virtual: https://events.vtools.ieee.org/m/273659 ORGANIZER:kasinski@agh.edu.pl SEQUENCE:2 SUMMARY:IC Chip and Packaging Interactions in Design for SI\, PI\, EMC and ESD URL;VALUE=URI:https://events.vtools.ieee.org/m/273659 X-ALT-DESC:Description: <br /><p><strong>Abstract:</strong></p>\n<p>Interac tions of IC chips and packaging structures differentiate the electronic pe rformance of power delivery networks (PDNs) in traditional 2D and advanced 2.5D and 3D technologies. This presentation discusses their impacts on si gnal integrity (SI)\, power integrity (PI)\, electromagnetic compatibility (EMC) and electrostatic discharge protection (ESD)\, through in-depth Si experiments with in-place noise measurements and full-chip level noise sim ulations. Test vehicles under study are given in traditional 2D face up an d flip chip packaging\, 2.5D fan-out wafer level packaging (FOWLP)\, and 3 D chip stacking with through silicon vias (TSVs).</p>\n<p><strong>Speaker' s Bio:</strong></p>\n<p style="font-weight: 400\;">Makoto Nagata received the B.S. and M.S. degrees in physics from Gakushuin University\, Tokyo\, i n 1991 and 1993\, respectively\, and a Ph.D. in electronics engineering fr om Hiroshima University\, Hiroshima\, in 2001. He was a research associate at Hiroshima University from 1994 to 2002\, an associate professor at Kob e University from 2002 to 2009 and promoted to a full professor in 2009. H e is currently a professor of the graduate school of science\, technology and innovation\, Kobe University\, Kobe\, Japan. He is a senior member of IEICE and IEEE.</p>\n<p style="font-weight: 400\;">His research interests include design techniques targeting high-performance mixed analog\, RF and digital VLSI systems with particular emphasis on power/signal/substrate i ntegrity and electromagnetic compatibility\, testing and diagnosis\, three -dimensional system integration\, as well as their applications for hardwa re security and safety.</p>\n<p style="font-weight: 400\;">Dr. Nagata has been a member of a variety of technical program committees of internationa l conferences such as the Symposium on VLSI Circuits (2002-2009)\, Custom Integrated Circuits Conference (2007-2009)\, Asian Solid-State Circuits Co nference (2005-2009)\, International Solid-State Circuits Conference (2014 -2017)\, European Solid-State Circuits Conference (2020-) and many others. He is chairing the Technology Directions subcommittee for International S olid-State Circuits Conference (2018-present). He is also serving as SSCS AdCom member (2020-). He is currently an associate editor for IEEE Transac tions on VLSI Systems (2015-present). He was a technical program chair (20 10-2011)\, a symposium chair (2012-2013) and an executive committee member (2014-2015) for the Symposium on VLSI circuits\, and also a chair for IEE E SSCS</p> END:VEVENT END:VCALENDAR