BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Asia/Calcutta BEGIN:STANDARD DTSTART:19451014T230000 TZOFFSETFROM:+0630 TZOFFSETTO:+0530 TZNAME:IST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20210710T124628Z UID:08AC7129-3C7B-460A-9126-7CB8D8C94B52 DTSTART;TZID=Asia/Calcutta:20210705T110000 DTEND;TZID=Asia/Calcutta:20210709T153000 DESCRIPTION:Dear Sir/ Madam\,\nThe Department of Electronics Engineering\, HBTU Kanpur is organising a\n05-Day Online National Level Faculty Developm ent Program (FDP) - cum - Short Term Training Programme (STTP)\n(TECHNICAL LY SPONSORED BY IEEE UP SECTION (INDIA))\n\non\n"Simulation\, Modelling\, and Application of Advanced Semiconductor Devices"\n\nDuration: 5 - 9\, Ju ly 2021\n\nThe objective of the program:\n- To deliver a diverse training program on semiconductor devices for students\, and young professionals.\n - To emphasize on modeling aspects and non-conventional analyses of semico nductor devices.\n- To deliver training on industrial device simulators fo r creating an opportunity to work on more focused problems of research.\n- To create awareness on applications of semiconductor devices\, and allied concepts.\n- To create an opportunity for the exchange of knowledge throu gh a common platform.\n\nTopics to be covered:\n\n- Historical perspective s of semiconductor devices\n- Fundamental concepts in semiconductor device s\n- Tunnel Field Effect Transistors: theory and modeling\n- FinFETs: theo ry and modeling\n- Statistical analyses of FinFETs\n- Thin-Film Transistor s: theory and modeling\n- Interdisciplinary aspects of semiconductor devic es\n- Applications of TFETs\n- Familiarization of Sentaurus TCAD.\n\nAll o ther details including the list of speakers are attached along with a deta iled program brochure.\n\nRegistration Link: Please may register yourself using the following google form link ( No Registration Fee )\n\nhttps://fo rms.gle/BJrX4UbAMGe4qpK16\n\nOnline platform to be used:\n\nThe Joining li nk (Google MEET) will be provided to the registered email ID of the partic ipants.\n\nNOTE:\n1. Closing of registration: 04.07.2021 or 250 participan ts whichever is earlier.\n2. Preference: Faculty/Industry person -> Resear ch Scholar -> PG Student -> UG Student\n\nCo-sponsored by: IEEE UP SECTION (INDIA)\n\nAgenda: \nSessions\n\nDay 1 | 05.07.2021\n\n11.00 a.m.-11.30 a .m. Inaugration\n\n11.30 a.m.-1.30p.m.\n\nLec 1: Evolution and fundamental s of semiconductor devices\n\n2.30 p.m.- 4.30 p.m.\n\nLec 2: Tunnel-FET & FinFET: needs\, performance aspects and statistical analysis\n\nDay 2 | 06 .07.2021\n\n10.00 a.m.- 11.00 a.m.\n\nLec 3: Modelling Strategies in FinFE T\n\n11.00 a.m.- 12.00 p.m.\n\nLec 4: Emerging FETs for Analog/RF Circuit Applications\n\n2.00 p.m.-3.00 p.m.\n\nLec 5: Modelling Approaches in TFET \n\n3.00 p.m.-4.00 p.m.\n\nHands-on/Demonstration 1: Familiarization of Sy nopsys TCAD ­­Tool\n\nDay 3 | 07.07.2021\n\n10.00 a.m.-12.00 p.m.\n\nLec 6: TFT: theory and modelling approaches\n\n2.00 p.m. -4.00 p.m.\n\nHands- on/Demonstration 2: Working on Sentaurus Structure Editor\n\nDay 4 | 08.07 .2021\n\n10.00 a.m.-12.00 p.m.\n\nLec 7: Interdisciplinary aspects of Semi conductor Devices\n\n2.00 p.m.-3.00 p.m:\n\nLec 8: Biosensors in Food Tech nology\n\n3.00 p.m.-4.00 p.m.:\n\nHands-on/Demonstration 3: Simulation & V isualization process in Synopsys TCAD\n\nDay 5 | 09.05.2021\n\n10.00 a.m.- 12.00 p.m.\n\nLec 9: TFET as Biosensors: theory and modelling approaches\n \n2.00 p.m.-3.00 p.m.:\n\nHands-on/Demonstration 4: Simulation and visuali zation of Advanced MOS Devices\n\n3.00 p.m.- 3.30 p.m. Valedictory session \n\nResource People :\n\n1. Prof. Partha Pratim Sahu (Senior Member\, IEEE )\, Professor at Department of Electronics and Communication Engineering\, Tezpur University\, Assam\, India\n\n2. Prof. Krishna Raj (Member-IEEE)\, Professor & HoD at Department of Electronics Engineering\, Harcourt Butle r Technical University Kanpur\, Uttar Pradesh\, India\n\n.3. Dr. N. B. Bal amurugan (Senior Member\, IEEE)\, Associate Professor at Department of Ele ctronics and Communication Engineering\, Thiagarajar College of Engineerin g Madurai\, Tamil Nadu\, INDIA\n\n4. Dr. Rupam Goswami (Member-IEEE)\, Ass istant Professor at Department of Electronics and Communication Engineerin g\, Tezpur University\, Assam\, India.\n\n5. Dr. Sunil Pandey Analog Desig n Engineer\, Intel Corporation\, India.\n\n6. Dr. Rajesh Saha (Senior Memb er\, IEEE)\, Assistant Professor at Department of Electronics and Communic ation Engineering\, MNIT Jaipur\, Rajasthan\, India.\n\n7. Dr. Kavindra Ka ndpal (Senior Member\, IEEE)\, Assistant Professor at the Electronics and Communication Engineering department of IIIT-Allahabad\n\n8. Dr. Suman Kum ar Mitra (Member-IEEE)\, Assistant Professor at Department of Electronics Engineering\, Harcourt Butler Technical University Kanpur\, Uttar Pradesh\ , India.\n\nVirtual: https://events.vtools.ieee.org/m/276362 LOCATION:Virtual: https://events.vtools.ieee.org/m/276362 ORGANIZER:skmitra@hbtu.ac.in SEQUENCE:1 SUMMARY:05-Day Online National Level Faculty Development Program (FDP) - cu m - Short Term Training Programme (STTP) on "Simulation\, Modelling\, and Application of Advanced Semiconductor Devices" URL;VALUE=URI:https://events.vtools.ieee.org/m/276362 X-ALT-DESC:Description: <br /><div>Dear Sir/ Madam\,</div>\n<div><strong>Th e Department of Electronics Engineering\, HBTU Kanpur is organising a&nbsp \;</strong></div>\n<div><span style="color: #e03e2d\;"><strong><span style ="font-size: large\;">05-Day Online National Level Faculty Development Pro gram (FDP) - cum - Short Term Training Programme (STTP)</span></strong></s pan></div>\n<div><strong>&nbsp\;(<span style="color: #000000\; font-family : arial\, sans-serif\;">TECHNICALLY SPONSORED&nbsp\;</span>BY&nbsp\;<span style="color: #000000\; font-family: arial\, sans-serif\;">IEEE UP SECTION (INDIA))</span></strong><strong><span style="font-size: large\;"><br /></ span></strong></div>\n<div><strong><span style="font-size: large\;">on</sp an></strong></div>\n<div><strong><span style="font-size: large\;"><span st yle="color: #3598db\;">"Simulation\, Modelling\, and Application of Advanc ed Semiconductor Devices"</span><br /></span></strong></div>\n<div><strong ><span style="font-size: large\;"><span style="color: #843fa1\;">Duration: 5 - 9\, July 2021</span></span></strong></div>\n<blockquote>\n<blockquote >\n<div><u>&nbsp\;</u></div>\n<div><strong><span style="color: #169179\;"> <u>The objective of the program:</u></span></strong></div>\n</blockquote>\ n</blockquote>\n<ul>\n<li>To deliver a diverse training program on semicon ductor devices for students\, and young professionals.</li>\n<li>To emphas ize on modeling aspects and non-conventional analyses of semiconductor dev ices.</li>\n<li>To deliver training on industrial device simulators for cr eating an opportunity to work on more focused problems of research.</li>\n <li>To create awareness on applications of semiconductor devices\, and all ied concepts.</li>\n<li>To create an opportunity for the exchange of knowl edge through a common platform.</li>\n</ul>\n<blockquote>\n<blockquote>\n< div><strong><u><span style="color: #9900ff\;">Topics to be covered:</span> </u></strong></div>\n</blockquote>\n</blockquote>\n<div>\n<ul>\n<li>Histor ical perspectives of semiconductor devices</li>\n<li>Fundamental concepts in semiconductor devices</li>\n<li>Tunnel Field Effect Transistors: theory and modeling</li>\n<li>FinFETs: theory and modeling</li>\n<li>Statistical analyses of FinFETs</li>\n<li>Thin-Film Transistors: theory and modeling< /li>\n<li>Interdisciplinary aspects of semiconductor devices</li>\n<li>App lications of TFETs</li>\n<li>Familiarization of Sentaurus TCAD.</li>\n</ul >\n<div><em><span style="color: #ff00ff\;"><strong>All other details inclu ding&nbsp\;the list of speakers are attached along with a detailed program brochure.</strong></span></em></div>\n<div>\n<div>\n<p><strong><span styl e="color: #ff0000\; font-size: large\;"><u>Registration Link</u>:</span><s pan style="color: #000000\; font-size: large\;">&nbsp\;Please may register yourself using the following google form link (</span></strong><span styl e="color: #ff0000\; font-size: large\;">&nbsp\;No Registration Fee&nbsp\;& nbsp\;</span><strong><span style="color: #000000\; font-size: large\;">)</ span></strong></p>\n<p><span style="color: #0000ff\; font-size: large\;">< a href="https://forms.gle/BJrX4UbAMGe4qpK16" target="_blank" rel="noopener noreferrer" data-saferedirecturl="https://www.google.com/url?q=https://fo rms.gle/BJrX4UbAMGe4qpK16&amp\;source=gmail&amp\;ust=1625208259879000&amp\ ;usg=AFQjCNEfSis1CAh0CR59p2jVRAyKBOlfjQ" data-mt-detrack-inspected="true"> https://forms.gle/<wbr />BJrX4UbAMGe4qpK16&nbsp\;&nbsp\;</a></span><strong ><u><span style="color: #ff00ff\;"><br /></span></u></strong></p>\n<p><em> <span style="font-family: arial black\, sans-serif\;"><strong><u><span sty le="color: #ff00ff\;">Online platform to be used:</span></u></strong><br / ></span></em></p>\n<p><span style="color: #000000\; font-family: arial bla ck\, sans-serif\;"><em>&nbsp\;The Joining link (</em></span><em>Google MEE T)&nbsp\;</em><span style="color: #000000\; font-family: arial black\, san s-serif\;"><em>will be provided&nbsp\;to the registered email ID of the&nb sp\;</em></span><em>participants.</em></p>\n</div>\n<div>&nbsp\;</div>\n<d iv><span style="color: #000000\; font-size: large\;">NOTE:&nbsp\;</span></ div>\n<div><span style="color: #000000\; font-size: large\;">1. Closing of registration:&nbsp\;04.07.2021&nbsp\;or 250 participants whichever is ear lier.</span></div>\n<div><span style="font-size: large\;"><span style="col or: #000000\;">2.</span><strong><span style="color: #0000ff\;">&nbsp\;</sp an></strong><strong><span style="color: #0000ff\;">Preference:&nbsp\;</spa n></strong>F</span>aculty/<wbr />Industry person -&gt\; Research Scholar - &gt\; PG Student -&gt\; UG Student</div>\n</div>\n</div>\n<div>&nbsp\;</di v><br /><br />Agenda: <br /><p class="_04xlpA direction-ltr align-center p ara-style-body"><span class="JsGRdQ">Sessions</span></p>\n<p class="_04xlp A direction-ltr align-center para-style-body">&nbsp\;</p>\n<p class="_04xl pA direction-ltr align-center para-style-body"><span class="JsGRdQ">Day 1 | 05.07.2021</span></p>\n<p class="_04xlpA direction-ltr align-justify par a-style-body"><span class="JsGRdQ">11.00 a.m.-11.30 a.m.</span> <span clas s="JsGRdQ">Inaugration</span></p>\n<p class="_04xlpA direction-ltr align-j ustify para-style-body"><span class="JsGRdQ">11.30 a.m.-1.30p.m.</span></p >\n<p class="_04xlpA direction-ltr align-justify para-style-body"><span cl ass="JsGRdQ">Lec 1:</span> <span class="JsGRdQ">Evolution and fundamentals of semiconductor devices</span></p>\n<p class="_04xlpA direction-ltr alig n-justify para-style-body"><span class="JsGRdQ">2.30 p.m.- 4.30 p.m.</span ></p>\n<p class="_04xlpA direction-ltr align-justify para-style-body"><spa n class="JsGRdQ">Lec 2: </span><span class="JsGRdQ">Tunnel-FET &amp\; FinF ET: needs\, performance aspects and statistical analysis</span></p>\n<p cl ass="_04xlpA direction-ltr align-center para-style-body"><span class="JsGR dQ">Day 2 | 06.07.2021</span></p>\n<p class="_04xlpA direction-ltr align-j ustify para-style-body"><span class="JsGRdQ">10.00 a.m.- 11.00 a.m.</span> </p>\n<p class="_04xlpA direction-ltr align-justify para-style-body"><span class="JsGRdQ">Lec 3: </span><span class="JsGRdQ">Modelling Strategies in FinFET</span></p>\n<p class="_04xlpA direction-ltr align-justify para-sty le-body"><span class="JsGRdQ">11.00 a.m.- 12.00 p.m.</span></p>\n<p class= "_04xlpA direction-ltr align-justify para-style-body"><span class="JsGRdQ" >Lec 4:</span> <span class="JsGRdQ">Emerging FETs for Analog/RF Circuit Ap plications</span></p>\n<p class="_04xlpA direction-ltr align-justify para- style-body"><span class="JsGRdQ">2.00 p.m.-3.00 p.m.</span></p>\n<p class= "_04xlpA direction-ltr align-justify para-style-body"><span class="JsGRdQ" >Lec 5:</span> <span class="JsGRdQ">Modelling Approaches in TFET</span></p >\n<p class="_04xlpA direction-ltr align-justify para-style-body"><span cl ass="JsGRdQ">3.00 p.m.-4.00 p.m.</span></p>\n<p class="_04xlpA direction-l tr align-justify para-style-body"><span class="JsGRdQ">Hands-on/Demonstrat ion 1:</span><span class="JsGRdQ"> Familiarization of Synopsys TCAD &shy\; &shy\;Tool</span></p>\n<p class="_04xlpA direction-ltr align-center para-s tyle-body"><span class="JsGRdQ">Day 3 | 07.07.2021</span></p>\n<p class="_ 04xlpA direction-ltr align-justify para-style-body"><span class="JsGRdQ">1 0.00 a.m.-12.00 p.m.</span></p>\n<p class="_04xlpA direction-ltr align-jus tify para-style-body"><span class="JsGRdQ">Lec 6:</span> <span class="JsGR dQ">TFT: theory and modelling approaches</span></p>\n<p class="_04xlpA dir ection-ltr align-justify para-style-body"><span class="JsGRdQ">2.00 p.m. - 4.00 p.m.</span></p>\n<p class="_04xlpA direction-ltr align-justify para-s tyle-body"><span class="JsGRdQ">Hands-on/Demonstration 2: </span><span cla ss="JsGRdQ">Working on Sentaurus Structure Editor</span></p>\n<p class="_0 4xlpA direction-ltr align-center para-style-body"><span class="JsGRdQ">Day 4 | 08.07.2021</span></p>\n<p class="_04xlpA direction-ltr align-justify para-style-body">&nbsp\;</p>\n<p class="_04xlpA direction-ltr align-justif y para-style-body"><span class="JsGRdQ">10.00 a.m.-12.00 p.m.</span></p>\n <p class="_04xlpA direction-ltr align-justify para-style-body"><span class ="JsGRdQ">Lec 7:</span> <span class="JsGRdQ">Interdisciplinary aspects of Semiconductor Devices</span></p>\n<p class="_04xlpA direction-ltr align-ju stify para-style-body"><span class="JsGRdQ">2.00 p.m.-3.00 p.m:</span></p> \n<p class="_04xlpA direction-ltr align-justify para-style-body"><span cla ss="JsGRdQ">Lec 8:</span> <span class="JsGRdQ">Biosensors in Food Technolo gy</span></p>\n<p class="_04xlpA direction-ltr align-justify para-style-bo dy"><span class="JsGRdQ">3.00 p.m.-4.00 p.m.:</span></p>\n<p class="_04xlp A direction-ltr align-justify para-style-body"><span class="JsGRdQ">Hands- on/Demonstration 3:</span> <span class="JsGRdQ">Simulation &amp\; Visualiz ation process in Synopsys TCAD</span></p>\n<p class="_04xlpA direction-ltr align-center para-style-body"><span class="JsGRdQ">Day 5 | 09.05.2021</sp an></p>\n<p class="_04xlpA direction-ltr align-justify para-style-body"><s pan class="JsGRdQ">10.00 a.m.-12.00 p.m.</span></p>\n<p class="_04xlpA dir ection-ltr align-justify para-style-body"><span class="JsGRdQ">Lec 9:</spa n> <span class="JsGRdQ">TFET as Biosensors: theory and modelling approache s</span></p>\n<p class="_04xlpA direction-ltr align-justify para-style-bod y"><span class="JsGRdQ">2.00 p.m.-3.00 p.m.:</span></p>\n<p class="_04xlpA direction-ltr align-justify para-style-body"><span class="JsGRdQ">Hands-o n/Demonstration 4:</span> <span class="JsGRdQ">Simulation and visualizatio n of Advanced MOS Devices</span></p>\n<p class="_04xlpA direction-ltr alig n-justify para-style-body"><span class="JsGRdQ">3.00 p.m.- 3.30 p.m.</span > <span class="JsGRdQ">Valedictory session</span></p>\n<p class="_04xlpA d irection-ltr align-justify para-style-body">&nbsp\;</p>\n<p class="_04xlpA direction-ltr align-center para-style-body"><span class="JsGRdQ">Resource People :</span></p>\n<p class="_04xlpA direction-ltr align-justify para-s tyle-body"><span class="JsGRdQ">1.</span> <span class="JsGRdQ">Prof. Parth a Pratim Sahu</span> <span class="JsGRdQ">(</span><span class="JsGRdQ">Sen ior Member\, IEEE)</span><span class="JsGRdQ">\, Professor at Department o f Electronics and Communication Engineering\, Tezpur University\, Assam\, India</span></p>\n<p class="_04xlpA direction-ltr align-justify para-style -body"><span class="JsGRdQ">2.</span><span class="JsGRdQ"> Prof. Krishna R aj </span><span class="JsGRdQ">(Member-IEEE)\,</span><span class="JsGRdQ"> Professor &amp\; HoD at Department of Electronics Engineering\, Harcourt Butler Technical University Kanpur\, Uttar Pradesh\, India</span></p>\n<p class="_04xlpA direction-ltr align-justify para-style-body"><span class="J sGRdQ">.</span><span class="JsGRdQ">3.</span> <span class="JsGRdQ">Dr. N. B. Balamurugan</span> <span class="JsGRdQ">(Senior Member\, IEEE)</span><s pan class="JsGRdQ">\, Associate Professor at Department of Electronics and Communication Engineering\, Thiagarajar College of Engineering Madurai\, Tamil Nadu\, INDIA</span></p>\n<p class="_04xlpA direction-ltr align-justi fy para-style-body"><span class="JsGRdQ">4</span><span class="JsGRdQ">. </ span><span class="JsGRdQ">Dr. Rupam Goswami </span><span class="JsGRdQ">(< /span><span class="JsGRdQ">Member-IEEE)</span><span class="JsGRdQ">\, Assi stant Professor at Department of Electronics and Communication Engineering \, Tezpur University\, Assam\, India.</span></p>\n<p class="_04xlpA direct ion-ltr align-justify para-style-body"><span class="JsGRdQ">5.</span> <spa n class="JsGRdQ">Dr. Sunil Pandey</span><span class="JsGRdQ"> Analog Desig n Engineer\, Intel Corporation\, India.</span></p>\n<p class="_04xlpA dire ction-ltr align-justify para-style-body"><span class="JsGRdQ">6.</span> <s pan class="JsGRdQ">Dr. Rajesh Saha </span><span class="JsGRdQ">(Senior Mem ber\, IEEE)\,</span><span class="JsGRdQ"> Assistant Professor at Departmen t of Electronics and Communication Engineering\, MNIT Jaipur\, Rajasthan\, India.</span></p>\n<p class="_04xlpA direction-ltr align-justify para-sty le-body"><span class="JsGRdQ">7. </span><span class="JsGRdQ">Dr. Kavindra Kandpal </span><span class="JsGRdQ">(Senior Member\, IEEE)\,</span><span c lass="JsGRdQ"> Assistant Professor at the Electronics and Communication En gineering department of IIIT-Allahabad</span></p>\n<p class="_04xlpA direc tion-ltr align-justify para-style-body"><span class="JsGRdQ">8</span><span class="JsGRdQ">. </span><span class="JsGRdQ">Dr. Suman Kumar Mitra</span> <span class="JsGRdQ">(Member-IEEE)\,</span><span class="JsGRdQ"> Assistan t Professor at Department of Electronics Engineering\, Harcourt Butler Tec hnical University Kanpur\, Uttar Pradesh\, India.</span></p> END:VEVENT END:VCALENDAR