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DTSTART:20210314T030000
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DTSTAMP:20210723T170058Z
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DTSTART;TZID=America/Los_Angeles:20210723T080000
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DESCRIPTION:Chiplet architecture is now becoming mainstream\, and recognize
 d as fundamental to enabling the continued economically viable growth of p
 ower efficient computing. We will cover the benefits of these approaches i
 n enabling lower costs from smaller die combined with modularity to scale 
 performance and configuration\, taking examples from industry products. Th
 e costs of splitting and modularizing an SOC into chiplets will be discuss
 ed\, which include the high-bandwidth and low-latency communication requir
 ements between die\, overheads of testing and power-managing what used to 
 be individual SOC modules as standalone chips\, and engineering the packag
 e substrate to provide routing and power delivery resources for the comple
 x integration. Today’s solutions will be evaluated in the context of wha
 t will be required from packaging and silicon technologies over the next d
 ecade to achieve the true potential of chiplet architecture.\n\nAgenda: \n
 DATE / TIME\nFriday\, July 23\, 2021 @ 8:00-9:15am PDT\n\nSan Diego\, Cali
 fornia\, United States\, Virtual: https://events.vtools.ieee.org/m/276922
LOCATION:San Diego\, California\, United States\, Virtual: https://events.v
 tools.ieee.org/m/276922
ORGANIZER:jfshi@ieee.org
SEQUENCE:1
SUMMARY:Architecture and Technology Implications of a Chiplet-Based Future
URL;VALUE=URI:https://events.vtools.ieee.org/m/276922
X-ALT-DESC:Description: <br /><p>Chiplet architecture is now becoming mains
 tream\, and recognized as fundamental to enabling the continued economical
 ly viable growth of power efficient computing. &nbsp\;&nbsp\;We will cover
  the benefits of these approaches in enabling lower costs from smaller die
  combined with modularity to scale performance and configuration\, taking 
 examples from industry products.&nbsp\; The costs of splitting and modular
 izing an SOC into chiplets will be discussed\, which include the high-band
 width and low-latency communication requirements between die\, overheads o
 f testing and power-managing what used to be individual SOC modules as sta
 ndalone chips\, and engineering the package substrate to provide routing a
 nd power delivery resources for the complex integration.&nbsp\; Today&rsqu
 o\;s solutions will be evaluated in the context of what will be required f
 rom packaging and silicon technologies over the next decade to achieve the
  true potential of chiplet architecture.</p><br /><br />Agenda: <br /><div
 >DATE / TIME</div>\n<div>Friday\, July 23\, 2021&nbsp\;@ 8:00-9:15am PDT</
 div>
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