BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:US/Eastern BEGIN:DAYLIGHT DTSTART:20210314T030000 TZOFFSETFROM:-0500 TZOFFSETTO:-0400 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:EDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20211107T010000 TZOFFSETFROM:-0400 TZOFFSETTO:-0500 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:EST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20211209T193350Z UID:19BAB59B-F0E5-4D69-B34B-414D189BC690 DTSTART;TZID=US/Eastern:20210918T120000 DTEND;TZID=US/Eastern:20210918T143000 DESCRIPTION:Silicon-Based Millimeter-Wave Phased Arrays for 5G: Fundamental s to Future Trends\n\nAgenda: \nBodhisatwa Sadhu\n\nBIOGRAPHY\n\nBodhisatw a Sadhu received the B.E. degree in Electrical and Electronics Engineering from Birla Institute of Technology and Science – Pilani (BITS-Pilani) i n 2007\, and the Ph.D. degree in Electrical Engineering from the Universit y of Minnesota\, Minneapolis\, in 2012.\n\nHe is currently a Research Staf f Member with the RF/mm-wave Communication Circuits & Systems Group at IBM T. J. Watson Research Center\, Yorktown Heights\, NY\, USA\, and an Adjun ct Assistant Professor at Columbia University\, NY. At IBM\, he has led th e design and demonstration of the world’s first reported silicon-based 5 G phased array IC\, a low power 60GHz CMOS transceiver IC for 802.11ad com munications\, a software-defined phased array radio\, and a self-healing 2 5GHz low noise frequency synthesizer. He has authored and co-authored 15+ journal papers\, 30+ conference papers\, the book Cognitive Radio Receiver Front-Ends-RF/Analog Circuit Techniques (Springer\, 2014)\, and several b ook chapters. He holds 20 issued U.S. patents with 20+ pending. Dr. Sadhu currently serves as an IEEE MTT-S Distinguished Microwave Lecturer\, the R FIC Systems Applications sub-committee chair of IEEE RFIC Symposium\, TPC member of Wireless Subcommittee at IEEE ISSCC\, and has served as a Guest Editor of IEEE JSSC in 2017.\n\nDr. Sadhu is the recipient of the 2017 ISS CC Lewis Winner Award for Outstanding Paper (best paper award)\, the 2017 JSSC Best Paper Award\, the 2017 Pat Goldberg Memorial Award for the best paper in computer science\, electrical engineering\, and mathematics publi shed by IBM Research\, three IBM A-level Accomplishment awards\, nine IBM Patent Plateau Awards\, the University of Minnesota Graduate School Fellow ship in 2007\, 3M Science and Technology Fellowship in 2009\, the Universi ty of Minnesota Doctoral Dissertation Fellowship in 2011\, the BITS Pilani Silver Medal in 2007\, the BITS Pilani Merit Scholarship from 2004 to 200 7\, and stood 2nd in India in the Indian School Certificate (ISC) examinat ion in 2003. He was recognized as an IBM Master Inventor in 2017\, and was selected by the National Academy of Engineering for its Frontiers of Engi neering Symposium in 2020.\n\nPRESENTATION\n\nSILICON-BASED MILLIMETER-WAV E PHASED ARRAYS FOR 5G: FUNDAMENTALS TO FUTURE TRENDS\n\n5G cellular commu nications use millimeter-wave phased arrays to achieve high data rates and low latency. The majority of the 5G millimeter-wave infrastructure will b e partially or completely based on silicon technology. This talk will disc uss key aspects of silicon-based millimeter-wave phased-array module desig n and characterization. It will cover fundamentals of phased arrays\, prov ide an overview of phased array antenna modules using silicon technology\, and take a deep dive into an example 5G phased array antenna module. The talk will end with a peek into the future of 5G directional communications .\n\nBuffalo\, New York\, United States\, 14221\, Virtual: https://events. vtools.ieee.org/m/277323 LOCATION:Buffalo\, New York\, United States\, 14221\, Virtual: https://even ts.vtools.ieee.org/m/277323 ORGANIZER:jmmoskal@ieee.org SEQUENCE:5 SUMMARY:Silicon-Based Millimeter-Wave Phased Arrays for 5G: Fundamentals to Future Trends URL;VALUE=URI:https://events.vtools.ieee.org/m/277323 X-ALT-DESC:Description: <br /><p>Silicon-Based Millimeter-Wave Phased Array s for 5G: Fundamentals to Future Trends</p><br /><br />Agenda: <br /><p cl ass="yiv5492604267MsoNormal">Bodhisatwa Sadhu</p>\n<p class="yiv5492604267 MsoNormal">&nbsp\;</p>\n<div>\n<p class="yiv5492604267MsoNormal"><strong>B IOGRAPHY</strong></p>\n</div>\n<p class="yiv5492604267MsoNormal">Bodhisatw a Sadhu received the B.E. degree in Electrical and Electronics Engineering from Birla Institute of Technology and Science &ndash\;&nbsp\;Pilani (BIT S-Pilani) in 2007\, and the Ph.D. degree in Electrical Engineering from th e University of Minnesota\, Minneapolis\, in 2012.</p>\n<p class="yiv54926 04267MsoNormal">He is currently a Research Staff Member with the RF/mm-wav e Communication Circuits &amp\; Systems Group at IBM T. J. Watson Research Center\, Yorktown Heights\, NY\, USA\, and an Adjunct Assistant Professor at Columbia University\, NY. At IBM\, he has led the design and demonstra tion of the world&rsquo\;s first reported silicon-based 5G phased array IC \, a low power 60GHz CMOS transceiver IC for 802.11ad communications\, a s oftware-defined phased array radio\, and a self-healing 25GHz low noise fr equency synthesizer. He has authored and co-authored 15+ journal papers\, 30+ conference papers\, the book Cognitive Radio Receiver Front-Ends-RF/An alog Circuit Techniques (Springer\, 2014)\, and several book chapters. He holds 20 issued U.S. patents with 20+ pending. Dr. Sadhu currently serves as an IEEE MTT-S Distinguished Microwave Lecturer\, the RFIC Systems Appli cations sub-committee chair of IEEE RFIC Symposium\, TPC member of Wireles s Subcommittee at IEEE ISSCC\, and has served as a Guest Editor of IEEE JS SC in 2017.</p>\n<p class="yiv5492604267MsoNormal">Dr. Sadhu is the recipi ent of the 2017 ISSCC Lewis Winner Award for Outstanding Paper (best paper award)\, the 2017 JSSC Best Paper Award\, the 2017 Pat Goldberg Memorial Award for the best paper in computer science\, electrical engineering\, an d mathematics published by IBM Research\, three IBM A-level Accomplishment awards\, nine IBM Patent Plateau Awards\, the University of Minnesota Gra duate School Fellowship in 2007\, 3M Science and Technology Fellowship in 2009\, the University of Minnesota Doctoral Dissertation Fellowship in 201 1\, the BITS Pilani Silver Medal in 2007\, the BITS Pilani Merit Scholarsh ip from 2004 to 2007\, and stood 2<sup>nd</sup>&nbsp\;in India in the Indi an School Certificate (ISC) examination in 2003. He was recognized as an I BM Master Inventor in 2017\, and was selected by the National Academy of E ngineering for its Frontiers of Engineering Symposium in 2020.</p>\n<div>\ n<p class="yiv5492604267MsoNormal"><strong>PRESENTATION</strong></p>\n</di v>\n<p class="yiv5492604267MsoNormal"><strong><em>SILICON-BASED MILLIMETER -WAVE PHASED ARRAYS FOR 5G: FUNDAMENTALS TO FUTURE TRENDS</em></strong></p >\n<p class="yiv5492604267MsoNormal">5G cellular communications use millim eter-wave phased arrays to achieve high data rates and low latency. The ma jority of the 5G millimeter-wave infrastructure will be partially or compl etely based on silicon technology. This talk will discuss key aspects of s ilicon-based millimeter-wave phased-array module design and characterizati on. It will cover fundamentals of phased arrays\, provide an overview of p hased array antenna modules using silicon technology\, and take a deep div e into an example 5G phased array antenna module. The talk will end with a peek into the future of 5G directional communications.</p> END:VEVENT END:VCALENDAR