BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Asia/Calcutta BEGIN:STANDARD DTSTART:19451014T230000 TZOFFSETFROM:+0630 TZOFFSETTO:+0530 TZNAME:IST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20211117T043508Z UID:7CB750B6-EE73-471F-BDDA-FCB3D108498A DTSTART;TZID=Asia/Calcutta:20210809T090000 DTEND;TZID=Asia/Calcutta:20210813T170000 DESCRIPTION:Amidst these un-precedented COVID times\, nobody was expecting a virtual workshop for memory design that could have practical session and demonstrate the ability to design best in class memory cells virtually. B ut IEEE CAS Bangalore Chapter took the challenge head-on by announcing in association with IEEE Bangalore Section “Memory Design Workshop (MDW) -2 021”. The team not just succeeded but got an astounding response from In dustry and Academia throughout the lecture and lab sessions.\n\nThe event was comprised of 5 days of lectures\,2 in a day from Industry maestros and esteemed academicians\, followed by self-paced hands-on lab session spann ing over 2 weeks.\n\nRegistration for the event started with an early bird discount of 50% discount for all registrations and as the registrations c losed the team had around 190+ registrations.\n\nEach day had an inaugural keynote followed by a technical session. Day one was special\, so the pro ceeding started of with an auspicious lighting of the lamp by the dignitar ies and the IEEE CAS Team.\n\nThe keynotes were delivered by IEEE veterans including the likes of IEEE Bangalore Section Chair - Mr. Bindhumadhav\, Vice Chair IEEE India Council – Mr. Puneet Mishra\, IEEE CASS President – Prof. Amara and IEEE CAS Vice President – Prof. Nishio.\n\nOne of th e inaugural sessions became the most memorable as Prof. Nishio announced a nd awarded the IEEE CAS Bangalore Chapter with “IEEE CAS Society 2021 - Chapter of the Year Award” making it the “Best CASS Chapter out of 121 chapters”.\n\nThe topics of the lecture for the memory design workshop was centred around how design enthusiasts can make the best-in-class memor y cells. The technical introduction was with all the different types of me mories which was delineated by Mr. Krishnan who covered from every memory type and its applications and it was a perfect setting of stage for the to pics to come over the entire week. Following days were in depth understand ing of the advanced subject of STT-RAM by industry greats like Mr. Siddhar th Gupta of ARM and Mr. Siva Kumar of Global Foundaries. There were sessio ns which explained about the Yield analysis of SRAM and math behind every Yield engineers mind. Then was the most interesting of all\, the use memor y in Neuro Morphic Computing by Prof. Durga Mishra of New Jersey Institute of Technology and In-Memory Compute by Prof. Manan Suri of Indian Institu te of Technology\, Delhi. We switched gears now to know the overview of LP DDR4 and Embedded Non-Volatile memories which was delivered by Mr. Venkat Bringi of Micron and Mr. Devraj of Texas Instruments\, respectively. To si gn-off the event\, we had to understand how we test and keep the security aspect in this highly illicit society\, so we had Mr. Ashish Kumar of ST-M icroelectronics brief about memory applications in security followed by Mr . Sanjith Sleeba of Nvidia\, who explained MBIST a mechanism for memory te st.\n\nAll the sessions were highly applauded by the virtual audience who throughout the week was interactive and involved.\n\nEach technical lectur e session had minimum of 100 attendees and a max for 143 was seen with lec tures spanning between 60 & 120 minutes.\n\nVirtual: https://events.vtools .ieee.org/m/278652 LOCATION:Virtual: https://events.vtools.ieee.org/m/278652 ORGANIZER:d.dwivedi@ieee.org SEQUENCE:1 SUMMARY:Memory Design Workshop 2021 (MDW) 9th to 13th\, August 2021 (VIRTUA L) URL;VALUE=URI:https://events.vtools.ieee.org/m/278652 X-ALT-DESC:Description: <br /><p><span style="font-weight: 400\;">Amidst th ese un-precedented COVID times\, nobody was expecting a virtual workshop f or memory design that could have practical session and demonstrate the abi lity to design best in class memory cells virtually. But IEEE CAS Bangalor e Chapter took the challenge head-on by announcing in association with IEE E Bangalore Section &ldquo\;Memory Design Workshop (MDW) -2021&rdquo\;. Th e team not just succeeded but got an astounding response from Industry and Academia throughout the lecture and lab sessions.&nbsp\;</span></p>\n<p>< span style="font-weight: 400\;">The event was comprised of 5 days of lectu res\,2 in a day from Industry maestros and esteemed academicians\, followe d by self-paced hands-on lab session spanning over 2 weeks.</span></p>\n<p ><span style="font-weight: 400\;">Registration for the event started with an early bird discount of 50% discount for all registrations and as the re gistrations closed the team had around 190+ registrations.</span></p>\n<p> <span style="font-weight: 400\;">Each day had an inaugural keynote followe d by a technical session. Day one was special\, so the proceeding started of with an auspicious lighting of the lamp by the dignitaries and the IEEE CAS Team.</span></p>\n<p><span style="font-weight: 400\;">The keynotes we re delivered by IEEE veterans including the likes of IEEE Bangalore Sectio n Chair - Mr. Bindhumadhav\, Vice Chair IEEE India Council &ndash\; Mr. Pu neet Mishra\, IEEE CASS President &ndash\; Prof. Amara and IEEE CAS Vice P resident &ndash\; Prof. Nishio.</span></p>\n<p><span style="font-weight: 4 00\;">One of the inaugural sessions became the most memorable as Prof. Nis hio announced and awarded the IEEE CAS Bangalore Chapter with &ldquo\;</sp an><strong><em>IEEE CAS Society 2021 - Chapter of the Year Award</em></str ong><span style="font-weight: 400\;">&rdquo\; making it the &ldquo\;</span ><strong>Best CASS Chapter out of 121 chapters</strong><span style="font-w eight: 400\;">&rdquo\;.</span></p>\n<p><span style="font-weight: 400\;">Th e topics of the lecture for the memory design workshop was centred around how design enthusiasts can make the best-in-class memory cells. The techni cal introduction was with all the different types of memories which was de lineated by Mr. Krishnan who covered from every memory type and its applic ations and it was a perfect setting of stage for the topics to come over t he entire week. Following days were in depth understanding of the advanced subject of STT-RAM by industry greats like Mr. Siddharth Gupta of ARM and Mr. Siva Kumar of Global Foundaries. There were sessions which explained about the Yield analysis of SRAM and math behind every Yield engineers min d. Then was the most interesting of all\, the use memory in Neuro Morphic Computing by Prof. Durga Mishra of New Jersey Institute of Technology and In-Memory Compute by Prof. Manan Suri of Indian Institute of Technology\, Delhi. We switched gears now to know the overview of LPDDR4 and Embedded N on-Volatile memories which was delivered by Mr. Venkat Bringi of Micron an d Mr. Devraj of Texas Instruments\, respectively. To sign-off the event\, we had to understand how we test and keep the security aspect in this high ly illicit society\, so we had Mr. Ashish Kumar of ST-Microelectronics bri ef about memory applications in security followed by Mr. Sanjith Sleeba of Nvidia\, who explained MBIST a mechanism for memory test.</span></p>\n<p> <span style="font-weight: 400\;">All the sessions were highly applauded by the virtual audience who throughout the week was interactive and involved .</span></p>\n<p><span style="font-weight: 400\;">Each technical lecture s ession had minimum of 100 attendees and a max for 143 was seen with lectur es spanning between 60 &amp\; 120 minutes.</span></p> END:VEVENT END:VCALENDAR