BEGIN:VCALENDAR
VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
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TZID:Asia/Dhaka
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DTSTART:20380119T091407
TZOFFSETFROM:+0600
TZOFFSETTO:+0600
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BEGIN:STANDARD
DTSTART:20091231T230000
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BEGIN:VEVENT
DTSTAMP:20210902T171803Z
UID:3A287109-247D-4CD6-A3A7-5A1D7FF634D9
DTSTART;TZID=Asia/Dhaka:20210811T183000
DTEND;TZID=Asia/Dhaka:20210811T200000
DESCRIPTION:Abstract of the Talk:\nThe ongoing scaling of CMOS technology i
 s now reaching its limit\, due to supply voltage reduction being restricte
 d by the subthreshold swing (SS) of 60mV/decade achievable at room tempera
 ture owing to Boltzmann transport of the charge carriers. Concept of negat
 ive capacitance proposed to achieve a sub-60mV/decade SS is currently seen
  as one of the potential solutions to the problem. A “negative capacitan
 ce transistor (NCFET)” employs a ferroelectric material in the gate stac
 k of a FET providing a negative capacitance and thereby an “internal vol
 tage amplification” at the gate of the internal FET which helps in reduc
 ing SS. Several experiments have successfully demonstrated an improved SS 
 with the bulk MOSFET\, FinFET\, and 2D FETs. The improvement in subthresho
 ld characteristics is also accompanied with the advantage of an increased 
 ON current relative to the reference FET as has been observed both in simu
 lation studies and experiments. In this talk\, our honorable speaker will 
 discuss the physics and modeling of various NCFET structures and impact of
  this new transistor on circuits including processors.\n\nSpeaker(s): Dr. 
 Yogesh Singh Chauhan\, \n\nVirtual: https://events.vtools.ieee.org/m/27899
 2
LOCATION:Virtual: https://events.vtools.ieee.org/m/278992
ORGANIZER:ieeeedssbcdu@gmail.com
SEQUENCE:6
SUMMARY:Modeling and Simulation of Negative Capacitance Transistors
URL;VALUE=URI:https://events.vtools.ieee.org/m/278992
X-ALT-DESC:Description: <br /><p><span class="d2edcug0 hpfvmrgz qv66sw1b c1
 et5uql b0tq1wua a8c37x1j keod5gw0 nxhoafnm aigsh9s9 d9wwppkn fe6kdd0r mau5
 5g9w c8b282yb hrzyx87i gfeo3gy3 a3bd9o3v knj5qynh oo9gr5id" dir="auto"><st
 rong>Abstract of the Talk: </strong><br />The ongoing scaling of CMOS tech
 nology is now reaching its limit\, due to supply voltage reduction being r
 estricted by the subthreshold swing (SS) of 60mV/decade achievable at room
  temperature owing to Boltzmann transport of the charge carriers. Concept 
 of negative capacitance proposed to achieve a sub-60mV/decade SS is curren
 tly seen as one of the potential solutions to the problem. A &ldquo\;negat
 ive capacitance transistor (NCFET)&rdquo\; employs a ferroelectric materia
 l in the gate stack of a FET providing a negative capacitance and thereby 
 an &ldquo\;internal voltage amplification&rdquo\; at the gate of the inter
 nal FET which helps in reducing SS. Several experiments have successfully 
 demonstrated an improved SS with the bulk MOSFET\, FinFET\, and 2D FETs. T
 he improvement in subthreshold characteristics is also accompanied with th
 e advantage of an increased ON current relative to the reference FET as ha
 s been observed both in simulation studies and experiments. In this talk\,
  our honorable speaker will discuss the physics and modeling of various NC
 FET structures and impact of this new transistor on circuits including pro
 cessors.</span></p>
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