BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/Sao_Paulo BEGIN:DAYLIGHT DTSTART:20380119T001407 TZOFFSETFROM:-0300 TZOFFSETTO:-0300 RRULE:FREQ=YEARLY;BYDAY=3TU;BYMONTH=1 TZNAME:-03 END:DAYLIGHT BEGIN:STANDARD DTSTART:20190216T230000 TZOFFSETFROM:-0200 TZOFFSETTO:-0300 RRULE:FREQ=YEARLY;BYDAY=3SA;BYMONTH=2 TZNAME:-03 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20211222T134044Z UID:634F7E6A-41FC-4004-96DF-B1246A133B53 DTSTART;TZID=America/Sao_Paulo:20210910T133000 DTEND;TZID=America/Sao_Paulo:20210910T153000 DESCRIPTION:Abstract:\n\nIn recent years\, Deep Neural Networks (DNNs) have made inroads into a number of applications involving pattern recognition ranging from facial recognition to self-driving cars. Many of these applic ations\, such as self-driving cars\, have real-time requirements\, where s pecialized DNN hardware accelerators help meet those requirements. As the models become more capable\, they also become deeper and more complex\, le ading to increased computational and storage demands. Model pruning and da ta quantization are two effective methods for mitigating this demand by co mpressing the network and simplifying computation. As hardware accelerator s push the performance envelope while adhering to strict power constraints \, reliability is frequently a casualty. In particular\, power-constrained DNN accelerators are more vulnerable to transient and intermittent hardwa re faults due to particle hits\, manufacturing variations\, and fluctuatio ns in power supply voltage and temperature. In this talk\, we will discuss reliability of DNNs from various design perspectives and share results fr om recent improvements.\n\nShort Bio:\n\nSandip Kundu is a Professor of El ectrical and Computer Engineering at the University of Massachusetts Amher st. Recently\, he also served as a program director at the National Scienc e Foundation. Kundu began his career at IBM Research as a Research Staff M ember\; then worked at Intel Corporation as a Principal Engineer before jo ining UMass Amherst as a professor in 2005. He has published nearly 300 re search papers in VLSI design and test\, holds several key patents includin g ultra-drowsy sleep mode in processors\, and has given more than a dozen tutorials at various conferences. He is a Fellow of the IEEE\, Fellow of t he Japan Society for Promotion of Science (JSPS)\, Senior International Sc ientist of the Chinese Academy of Sciences and was a Distinguished Visitor of the IEEE Computer Society. He has served as associate editor of a numb er of IEEE and ACM journals. He has been the Technical Program Chair/Gener al Chair of multiple conferences including ICCD\, ATS\, ISVLSI\, DFTS and VLSI Design.\n\nVirtual: https://events.vtools.ieee.org/m/279993 LOCATION:Virtual: https://events.vtools.ieee.org/m/279993 ORGANIZER:jose.azambuja@inf.ufrgs.br SEQUENCE:1 SUMMARY:CASS Talks with Sandip Kundu\, University of Massachusetts Amherst\ , USA URL;VALUE=URI:https://events.vtools.ieee.org/m/279993 X-ALT-DESC:Description: <br /><p>&nbsp\;</p>\n<p>&nbsp\;</p>\n<p>Abstract:< /p>\n<p>In recent years\, Deep Neural Networks (DNNs) have made inroads in to a number of&nbsp\;applications involving pattern recognition ranging fr om facial recognition to self-driving cars.&nbsp\;Many of these applicatio ns\, such as self-driving cars\, have real-time requirements\, where&nbsp\ ;specialized DNN hardware accelerators help meet those requirements. As th e models&nbsp\;become more capable\, they also become deeper and more comp lex\, leading to increased&nbsp\;computational and storage demands. Model pruning and data quantization are two effective&nbsp\;methods for mitigati ng this demand by compressing the network and simplifying&nbsp\;computatio n. As hardware accelerators push the performance envelope while adhering t o&nbsp\;strict power constraints\, reliability is frequently a casualty. I n particular\, power-constrained&nbsp\;DNN accelerators are more vulnerabl e to transient and intermittent hardware faults due to&nbsp\;particle hits \, manufacturing variations\, and fluctuations in power supply voltage and &nbsp\;temperature. In this talk\, we will discuss reliability of DNNs fro m various design&nbsp\;perspectives and share results from recent improvem ents.&nbsp\;</p>\n<p>Short Bio:&nbsp\;</p>\n<p>Sandip&nbsp\;<span class="m arkbufuz89as" data-markjs="true" data-ogac="" data-ogab="" data-ogsc="" da ta-ogsb="">Kundu</span>&nbsp\;is a Professor of Electrical and Computer En gineering at the University of&nbsp\;Massachusetts Amherst. Recently\, he also served as a program director at the National&nbsp\;Science Foundation .&nbsp\;<span class="markbufuz89as" data-markjs="true" data-ogac="" data-o gab="" data-ogsc="" data-ogsb="">Kundu</span>&nbsp\;began his career at IB M Research as a Research Staff Member\;&nbsp\;then worked at Intel Corpora tion as a Principal Engineer before joining UMass Amherst as a&nbsp\;profe ssor in 2005. He has published nearly 300 research papers in VLSI design a nd test\,&nbsp\;holds several key patents including ultra-drowsy sleep mod e in processors\, and has given&nbsp\;more than a dozen tutorials at vario us conferences. He is a Fellow of the IEEE\, Fellow of the&nbsp\;Japan Soc iety for Promotion of Science (JSPS)\, Senior International Scientist of t he Chinese&nbsp\;Academy of Sciences and was a Distinguished Visitor of th e IEEE Computer Society. He has&nbsp\;served as associate editor of a numb er of IEEE and ACM journals. He has been the Technical&nbsp\;Program Chair /General Chair of multiple conferences including ICCD\, ATS\, ISVLSI\, DFT S&nbsp\;and VLSI Design.</p> END:VEVENT END:VCALENDAR