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DTSTART:20220313T030000
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DTSTART:20211107T010000
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DTSTAMP:20211112T010214Z
UID:B8EB53E4-A201-495B-9589-2D1E5F7C7DC0
DTSTART;TZID=US/Eastern:20211111T120000
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DESCRIPTION:The Electron Devices Society (EDS)\, Northern Virginia/Washingt
 on Jt. Sections Chapters joined with The Nanotechology Council (NTC) are p
 leased to host an EDS Distinguished Lecture presented by Prof. Shimeng Yu\
 , School of Electrical and Computer Engineering\, Georgia Institute of Tec
 hnology.\n\nPlease register to receive the WebEx link the day before the e
 vent.\n\n-----------------------------------------------------------------
 -------------\n\nAnalog multilevel memories are the enabling device techno
 logies for hardware acceleration of neuro-inspired computing workloads. In
  this lecture\, we will survey the landscape of the emerging non-volatile 
 memories that could serve the synaptic weights with a focus on resistive a
 nd ferroelectric devices. We will highlight the key device properties that
  are required for on-chip inference and/or training of deep neural network
  (DNN) models. We will use a multi-bit RRAM test vehicle to characterize t
 he variability/reliability at array-level for inference. Then we will intr
 oduce an end-to-end benchmark framework DNN+NeuroSim to that is interfaced
  with PyTorch to evaluate versatile device technologies for DNN inference.
  Hybrid precision synapse that combines non-volatile memories with volatil
 e capacitor is also presented to achieve in-situ training accuracy that is
  comparable with software. We will also showcase the integration of RRAM w
 ith peripheral CMOS at 40nm for a complete compute-in-memory prototype chi
 p. Future research directions will be discussed.\n\nSpeaker(s): Prof. Shim
 eng Yu\, \n\nVirtual: https://events.vtools.ieee.org/m/284899
LOCATION:Virtual: https://events.vtools.ieee.org/m/284899
ORGANIZER:tonyguo@ieee.org
SEQUENCE:12
SUMMARY:Landscape of Synaptic Weight Memories
URL;VALUE=URI:https://events.vtools.ieee.org/m/284899
X-ALT-DESC:Description: &lt;br /&gt;&lt;div id=&quot;list_meeting_header&quot;&gt;\n&lt;p&gt;The Electr
 on Devices Society (EDS)\, Northern Virginia/Washington Jt. Sections Chapt
 ers joined with The Nanotechology Council (NTC) are pleased to host an EDS
  Distinguished Lecture presented by Prof. Shimeng Yu\, School of Electrica
 l and Computer Engineering\, Georgia Institute of Technology.&lt;/p&gt;\n&lt;p&gt;Plea
 se register to receive the WebEx link the day before the event.&lt;/p&gt;\n&lt;p&gt;--
 --------------------------------------------------------------------------
 --&lt;/p&gt;\n&lt;/div&gt;\n&lt;p&gt;Analog multilevel memories are the enabling device tech
 nologies for hardware acceleration of neuro-inspired computing workloads. 
 In this lecture\, we will survey the landscape of the emerging non-volatil
 e memories that could serve the synaptic weights with a focus on resistive
  and ferroelectric devices. We will highlight the key device properties th
 at are required for on-chip inference and/or training of deep neural netwo
 rk (DNN) models. We will use a multi-bit RRAM test vehicle to characterize
  the variability/reliability at array-level for inference. Then we will in
 troduce an end-to-end benchmark framework DNN+NeuroSim to that is interfac
 ed with PyTorch to evaluate versatile device technologies for DNN inferenc
 e. Hybrid precision synapse that combines non-volatile memories with volat
 ile capacitor is also presented to achieve in-situ training accuracy that 
 is comparable with software. We will also showcase the integration of RRAM
  with peripheral CMOS at 40nm for a complete compute-in-memory prototype c
 hip. Future research directions will be discussed.&amp;nbsp\;&lt;/p&gt;
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