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DTSTAMP:20220118T173043Z
UID:4DA82555-6E74-4B07-B3D9-E3076F020D11
DTSTART;TZID=Europe/Zurich:20211125T100000
DTEND;TZID=Europe/Zurich:20211125T113000
DESCRIPTION:---------------------------------------------------------------
 \n\nDear Members\,\n\nWe hope all of you are doing well and healthy\,\n\nY
 our Swiss Solid State Circuit Society chapter is please to host Lorenzo CE
 RATI\, Who is a Senior Member of the Technical Staff at ST Microelectronic
 s.\n\nThe video conferencing link will be provided on the day to registred
  attendees.\n\nThe topic of the lecture is : &quot; ESD Design in High Voltage 
 Smart Power Technologies &quot;\n\nPlease Join at 10:00 AM [CET] mute your head
 set or microphone.\n\nWe make a group picture in the begining for society 
 report.\n\nFor the Q&amp;A make sure to have your headset or a proper micropho
 ne.\n\nThe Agenda is as follow:\n\n10:00 - 10:05 Welcome participants Tele
 conference set-up\n\n10:05 - 11:15 Lecture\n\n11:15 - 11:30 Questions / Di
 scussion\n\nWe look forward meeting you and having fruitful discussion.\n\
 nKind regards\,\n\nMathieu Coustans\n\nFor your IEEE Switzerland Solid Sta
 te Circuit Society committee.\n\nSpeaker(s): Lorenzo CERATI\, \n\nVirtual:
  https://events.vtools.ieee.org/m/288586
LOCATION:Virtual: https://events.vtools.ieee.org/m/288586
ORGANIZER:mathieu.coutans@ieee.org
SEQUENCE:5
SUMMARY:IEEE SWISS SSC DISTINGUISHED LECTURE (WEBINAR) / ESD Design in High
  Voltage Smart Power Technologies
URL;VALUE=URI:https://events.vtools.ieee.org/m/288586
X-ALT-DESC:Description: &lt;br /&gt;&lt;hr class=&quot;hr-solid hr-extended ieee_bright_o
 range_bt2&quot; /&gt;\n&lt;p&gt;Dear Members\,&lt;/p&gt;\n&lt;p&gt;We hope all of you are doing well
  and healthy\,&lt;/p&gt;\n&lt;p&gt;Your Swiss Solid State Circuit Society chapter is p
 lease to host Lorenzo CERATI&lt;!--EndFragment --&gt;\, Who is a Senior Member o
 f the Technical Staff at ST Microelectronics.&lt;/p&gt;\n&lt;p&gt;The video conferenci
 ng link will be provided on the day to registred attendees.&lt;/p&gt;\n&lt;p&gt;The to
 pic of the lecture is : &quot;&amp;nbsp\;ESD Design in High Voltage Smart Power Tec
 hnologies &quot;&lt;/p&gt;\n&lt;p&gt;Please Join at 10:00 AM [CET] mute your headset or mic
 rophone.&lt;/p&gt;\n&lt;p&gt;We make a group picture in the begining for society repor
 t.&lt;/p&gt;\n&lt;p&gt;For the Q&amp;amp\;A make sure to have your headset or a proper mic
 rophone.&lt;/p&gt;\n&lt;p&gt;The Agenda is as follow:&lt;/p&gt;\n&lt;p&gt;10:00 - 10:05 Welcome pa
 rticipants Teleconference set-up&lt;/p&gt;\n&lt;p&gt;10:05 - 11:15 Lecture&lt;/p&gt;\n&lt;p&gt;11:
 15 - 11:30 Questions / Discussion&lt;/p&gt;\n&lt;p&gt;We look forward meeting you and 
 having fruitful discussion.&lt;/p&gt;\n&lt;p&gt;Kind regards\,&lt;/p&gt;\n&lt;p&gt;Mathieu Coustan
 s&lt;/p&gt;\n&lt;p&gt;For your IEEE Switzerland Solid State Circuit Society committee.
 &lt;/p&gt;
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