BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Asia/Calcutta BEGIN:STANDARD DTSTART:19451014T230000 TZOFFSETFROM:+0630 TZOFFSETTO:+0530 TZNAME:IST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20231223T161339Z UID:731C8781-BC2A-4AC3-B29B-F52F5C9C9006 DTSTART;TZID=Asia/Calcutta:20211120T140000 DTEND;TZID=Asia/Calcutta:20211120T153000 DESCRIPTION:About Ayyalasomayajula Lalitha:\n\nAyyalasomayajula Lalitha was India's first Woman Engineer\, graduated in 1943 in Electrical Engineerin g. She was born on 27 August 1919 in Chennai. She joined the Central Stand ards Organization in Shimla for a brief period.\n\nShe joined Associated E lectrical Industries and started designing transmission lines\, substation layout and executed various contracts. She was associated with the work o n electrical generators for the Bhakra Nangal Dam. In 1953\, the Council o f the Institution of Electrical Engineers (IEE)\, London elected her to be an associate member and in 1966 to a full member. She was the only woman engineer from India to attend the First International Conference of Women Engineers and Scientists (ICWES) in New York in June 1964. She was an acti ve volunteer in an international women engineering organization throughout her life. Lalitha’s life is a beacon of light for all the women who cam e after her in the 1950s to till date and her accomplishments inspire ever y woman.\n\nBrief Details about Lalitha Memorial Lecture (LML)\n\nIEEE-Hyd erabad Section and WIE AG jointly conducts every year a Lalitha Memorial L ecture. This is a Flagship event of our Section and IEEE Hyderabad Section Women in Engineering Affinity Group. Distinguished/ eminent women who con tributed to innovations\, applications of technology for the advancement o f our society\, are invited by us for our LML for delivering lectures to e nrich the knowledge of fellow professional engineers and students.\n\nBrie f Profile of the Invited Speaker:\n\nMs. Vijaya Durga\, is working as Scie ntist-G at RCI\, DRDO\, Hyderabad. She is Leading the team for ASICs and S oC (System on Chip) designs at RCI for sister labs NPOL\, NSTL\, & ASL etc . From the specifications to design realization with team\, testing\, fabr ication with industry\, prototype board development and proving the functi onality and design of embedded systems for different applications are the goals. She was also team member for first Indian chip ANUCO floating point co-processor in 1993. She has carried Architecture Design & development o f DRDO first DRDO indigenous ASIC-ANUCO & fabricated successfully in 1993 as team member at ANURAG. Her team received Indian Patent. She has also ca rried Design & simulations of ANUPAMA 32-bit indigenous processor in 1995 as a team member\, chip fabricated and tested successfully. She received L ab Level Team award from DRDO for first indigenous processor ANUPAMA in th e year 1996. She was involved in design of DPRAM based DDS Frequency Synth esisers completed & fabricated with Indian fab at SITAR in 1997. These chi ps are widely used in the SONAR systems for under water applications. Rece ived Lab level Scientist of the year award in 2000. As a Head of SOC wing at ANURAG\, design & development of System on Chips based on DSP cores and designing ASICs\, is leading a team of VLSI scientists for these activiti es and developed applications on to various SOCs/ASICs. She developed appl ication boards\, for ASICs/SOCs. These ASICs were subsequently used in pro duction systems by BEL\, BDL\, ECIL & L&T.Chips were designed from the var ious requirements given by CAIR\, DEAL \, NSTL & NPOL. DSP cores designed are 16-bit and 32-bit and CEVA processor integration. Many of the ASICs fa bricated at Indian fab using 1u technology at SITART are used in productio n systems. She also received Team lead award in yr 2007 at ANURAG. She is System Administrator for VLSI design & enhanced EDA set-up at ANURAG. She received DRDO Scientist of the year award from RM in the year 2010\, for u sage of various indigenous ASICs in End systems. She is Fellow of IETE\, M ember of IMAP Society. She has published many papers in national and inter national conferences and journals.\n\nRegistration and Joining Link: https ://bit.ly/LML-2021\n\nCo-sponsored by: Mr. Srinivas Jasti\, Chair\, IEEE-H yderabad Section \n\nSpeaker(s): Ms. Vijaya Durga\, \n\nAgenda: \n1. Welc ome address by Dr. Y. Padma Sai\, Chair\, IEEE WIE AG\, Hyderabad Section\ n\n2. Address by Mr. Srinivas Jasti\, Chair\, IEEE Hyderabad Section\n\n3. Talk by Ms. Vijaya Durga\, Scientist-G\, RCI\, DRDO\, Hyderabad\n\n4. Vot e of Thanks\n\nHyderabad\, Andhra Pradesh\, India\, Virtual: https://event s.vtools.ieee.org/m/288799 LOCATION:Hyderabad\, Andhra Pradesh\, India\, Virtual: https://events.vtool s.ieee.org/m/288799 ORGANIZER:padmasai_y@ieee.org SEQUENCE:4 SUMMARY:IEEE WIE AG in association with IEEE-Hyderabad Section/Fourth Flags hip event Lalitha Memorial Lecture (LML) on "SOC Design Challenges- Analog ous to DSP Systems" on 20th November\, 2021 from 2.00 PM to 3.30 PM (IST)   URL;VALUE=URI:https://events.vtools.ieee.org/m/288799 X-ALT-DESC:Description: <br /><p><strong>About Ayyalasomayajula Lalitha:</s trong></p>\n<p>Ayyalasomayajula Lalitha was India's first Woman Engineer\, graduated in 1943 in Electrical Engineering. She was born on 27 August 19 19 in Chennai. She joined the Central Standards Organization in Shimla for a brief period.</p>\n<p>She joined Associated Electrical Industries and s tarted designing transmission lines\, substation layout and executed vario us contracts. She was associated with the work on electrical generators fo r the Bhakra Nangal Dam. In 1953\, the Council of the Institution of Elect rical Engineers (IEE)\, London elected her to be an associate member and i n 1966 to a full member. She was the only woman engineer from India to att end the First International Conference of Women Engineers and Scientists ( ICWES) in New York in June 1964. She was an active volunteer in an interna tional women engineering organization throughout her life. Lalitha&rsquo\; s life is a beacon of light for all the women who came after her in the 19 50s to till date and her accomplishments inspire every woman.</p>\n<p><str ong>Brief Details about Lalitha Memorial Lecture (LML)</strong></p>\n<p>IE EE-Hyderabad Section and WIE AG jointly conducts every year a Lalitha Memo rial Lecture. This is a Flagship event of our Section and IEEE Hyderabad S ection Women in Engineering Affinity Group. Distinguished/ eminent women w ho contributed to innovations\, applications of technology for the advance ment of our society\, are invited by us for our LML for delivering lecture s to enrich the knowledge of fellow professional engineers and&nbsp\; stud ents.</p>\n<p><strong>Brief Profile of the Invited Speaker:</strong></p>\n <p><strong>Ms. Vijaya Durga\,</strong> is working as Scientist-G at RCI\, DRDO\, Hyderabad. She is Leading &nbsp\;the team for ASICs&nbsp\; and SoC (System on Chip) designs at RCI&nbsp\; for sister &nbsp\;labs NPOL\, NSTL\ , &amp\; ASL etc. From the specifications to&nbsp\; design realization wit h team\, testing\, fabrication with industry\, prototype board development and proving&nbsp\; the&nbsp\; functionality and design of embedded system s for different applications are the goals. She was also team member for f irst Indian chip ANUCO floating point co-processor in 1993. She has carrie d Architecture Design &amp\; development of DRDO first DRDO indigenous ASI C-ANUCO &amp\; fabricated successfully in 1993 as team member at ANURAG. H er team received Indian Patent. She has also carried Design &amp\; simulat ions of ANUPAMA 32-bit indigenous processor in 1995 as a team member\, chi p&nbsp\; fabricated and tested successfully. She received Lab Level Team a ward from DRDO for first indigenous processor ANUPAMA in the year 1996.&nb sp\; She was involved in design of DPRAM based DDS Frequency Synthesisers& nbsp\; completed &amp\; fabricated with Indian fab at SITAR in 1997. These chips are widely used in the SONAR systems for under water applications. Received Lab level Scientist of the year award in 2000.&nbsp\;As a Head of &nbsp\; SOC wing at ANURAG\, design &amp\; development of System on Chips based on DSP cores and designing ASICs\, is leading a team of VLSI scienti sts for these activities&nbsp\; and developed applications on to various S OCs/ASICs.&nbsp\; She developed application boards\, for ASICs/SOCs. These ASICs were subsequently&nbsp\; used in production systems by BEL\, BDL\, ECIL &amp\; L&amp\;T.Chips were designed from the various requirements giv en by CAIR\, DEAL \, NSTL &amp\; NPOL. DSP cores designed are 16-bit and 3 2-bit and CEVA processor integration. Many of the ASICs fabricated at Indi an fab using 1u technology at SITART are used in production systems.&nbsp\ ; She also received Team lead award in yr 2007 at ANURAG. She is System Ad ministrator for VLSI design &amp\; enhanced EDA set-up at ANURAG. She rece ived DRDO Scientist of the year award from RM in the year 2010\, for usage of various indigenous ASICs in End systems. She is Fellow of IETE\, Membe r of IMAP Society. She has published many papers in national and internati onal conferences and journals.</p>\n<p>&nbsp\;</p>\n<p>&nbsp\;</p>\n<p>Reg istration and Joining Link: https://bit.ly/LML-2021</p><br /><br />Agenda: <br /><p>1. Welcome address by Dr. Y. Padma Sai\, Chair\, IEEE WIE AG\, H yderabad Section</p>\n<p>2. Address by Mr. Srinivas Jasti\, Chair\, IEEE H yderabad Section</p>\n<p>3. Talk by Ms. Vijaya Durga\, Scientist-G\, RCI\, DRDO\, Hyderabad</p>\n<p>4. Vote of Thanks</p> END:VEVENT END:VCALENDAR