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DTSTART:20220313T030000
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DTSTART:20211107T010000
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BEGIN:VEVENT
DTSTAMP:20211210T180043Z
UID:2BC60671-91E6-4D3E-B4F0-71D7FB98A55E
DTSTART;TZID=America/Los_Angeles:20211210T080000
DTEND;TZID=America/Los_Angeles:20211210T100000
DESCRIPTION:The tutorial starts with a basic/introductive overview of moder
 n frequency synthesis techniques\, delivering basic operation theory in an
  intuitive fashion. A point of attention is in this context brought to rec
 ent subsampling PLL architecture. This architecture overcomes the performa
 nce boundaries typically encountered in classical implementations and is r
 edefining today’s state-of-the state of art in frequency synthesis. We w
 ill try to explain why. The following part of the tutorial explores the su
 bsampling loop in context of state-of-the art fractional synthesis and pha
 se modulation. We show how to enable fractional-N multiplication modes\, w
 hile retaining benefits of low-noise subsampling operation. This can be ac
 hieved by introducing digital-to-time converter (DTC)-based time domain si
 gnal processing. We will discuss potential limitations of this block\, and
  how to overcome them in the analog\, or in the digital domain. The versat
 ility of the DTC-based subsampling PLL will further be discussed in contex
 t of phase/frequency modulation\, which is crucial for accurate polar sign
 aling. We will investigate classical loop-bandwidth limitations and explor
 e how two-point modulation principles can elegantly be applied in context 
 of the explored loop. We will openly discuss potential weak-points of this
  environment – and how to address them. This talk insists on an intuitiv
 e\, rather than a strict\, mathematical approach to PLLs. It starts from t
 he basic concepts and then gradually expands in complexity\, while clearly
  highlighting the key ideas and pointing to state-of-the-art embodiments.\
 n\nVirtual: https://events.vtools.ieee.org/m/292086
LOCATION:Virtual: https://events.vtools.ieee.org/m/292086
ORGANIZER:jfshi@ieee.org
SEQUENCE:1
SUMMARY:Subsampling PLLs for Frequency Synthesis and Phase Modulation
URL;VALUE=URI:https://events.vtools.ieee.org/m/292086
X-ALT-DESC:Description: &lt;br /&gt;&lt;p&gt;The tutorial starts with a basic/introduct
 ive overview of modern frequency synthesis&amp;nbsp\;techniques\, delivering b
 asic operation theory in an intuitive fashion. A point of attention is in 
 this context brought to recent subsampling PLL architecture. This architec
 ture overcomes the performance boundaries typically encountered in classic
 al implementations and is redefining today&amp;rsquo\;s state-of-the state of 
 art in frequency synthesis. We will try to explain why. The following part
  of the tutorial explores the subsampling loop in context of state-of-the 
 art fractional synthesis and phase modulation. We show how to enable fract
 ional-N multiplication modes\, while retaining benefits of low-noise subsa
 mpling operation. This can be achieved by introducing digital-to-time conv
 erter (DTC)-based time domain signal processing. We will discuss potential
  limitations of this block\, and how to overcome them in the analog\, or i
 n the digital domain. The versatility of the DTC-based subsampling PLL wil
 l further be discussed in context of phase/frequency modulation\, which is
  crucial for accurate polar signaling. We will investigate classical loop-
 bandwidth limitations and explore how two-point modulation principles can 
 elegantly be applied in context of the explored loop. We will openly discu
 ss potential weak-points of this environment &amp;ndash\; and how to address t
 hem.&amp;nbsp\;This talk insists on an intuitive\, rather than a strict\, math
 ematical approach to PLLs. It starts from the basic concepts and then grad
 ually expands in complexity\, while clearly highlighting the key ideas and
  pointing to state-of-the-art embodiments.&lt;/p&gt;
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