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BEGIN:VEVENT
DTSTAMP:20211217T153535Z
UID:444C2BDE-C693-4021-B01E-F9766A66DF26
DTSTART;TZID=Europe/Stockholm:20211217T153000
DTEND;TZID=Europe/Stockholm:20211217T163000
DESCRIPTION:Fully depleted silicon-on-insulator (FDSOI) CMOS with thick bur
 ied oxide can operate at higher temperatures compared to bulk CMOS. This w
 ork demonstrates\, both experimentally and through simulations\, that the 
 subthreshold characteristics (off-state leakage current and subthreshold s
 wing\, SS) are improved at high temperatures by reducing the Si thickness 
 in FDSOI CMOS. Fabricated N and PFET devices exhibits an off-state leakage
  current less than 300 pA/µm and close to an ideal subthreshold swing of 
 less than 132 mV/dec. at 300 °C. TCAD simulations closely match measured 
 data and show that electrostatic control of the Si layer is key to achieve
  close to ideal subthreshold swing and low off-state current. With proper 
 gate electrodes FDSOI CMOS can achieve an Ioff < 1nA/µm at 300 °C for bo
 th P and NFETs. Ring oscillator simulations\, using an UTSOI compact model
  calibrated to fabricated devices\, demonstrate functional behavior at 300
  C with 2.2 times increased propagation delay compared to room temperat
 ure operation. This result shows that FDSOI CMOS can find use as low power
  control logic at high temperatures.\n\nSpeaker(s): Assoc. Prof. Per-Erik 
 Hellström\, \n\nVirtual: https://events.vtools.ieee.org/m/294765
LOCATION:Virtual: https://events.vtools.ieee.org/m/294765
ORGANIZER:bellman@kth.se
SEQUENCE:2
SUMMARY:Si thickness influence on subthreshold currents at high temperature
 s in FDSOI CMOS
URL;VALUE=URI:https://events.vtools.ieee.org/m/294765
X-ALT-DESC:Description: <br /><p>Fully depleted silicon-on-insulator (FDSOI
 ) CMOS with thick buried oxide can operate at higher temperatures compared
  to bulk CMOS. This work demonstrates\, both experimentally and through si
 mulations\, that the subthreshold characteristics (off-state leakage curre
 nt &nbsp\;and subthreshold swing\, SS) are improved at high temperatures b
 y reducing the Si thickness &nbsp\;in FDSOI CMOS. Fabricated N and PFET de
 vices exhibits an off-state leakage current less than 300 pA/&micro\;m and
  close to an ideal subthreshold swing of less than 132 mV/dec. at 300 &deg
 \;C. TCAD simulations closely match measured data and show that electrosta
 tic control of the Si layer is key to achieve close to ideal subthreshold 
 swing and low off-state current. With proper gate electrodes FDSOI CMOS ca
 n achieve an Ioff &lt\; 1nA/&micro\;m at 300 &deg\;C for both P and NFETs.
  Ring oscillator simulations\, using an UTSOI compact model calibrated to 
 fabricated devices\, demonstrate functional behavior at 300 C with 2.2 
 times increased propagation delay compared to room temperature operation. 
 This result shows that FDSOI CMOS can find use as low power control logic 
 at high temperatures.</p>
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