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DTSTAMP:20220124T133712Z
UID:3C97DBB6-A7D4-49F1-A257-915648775A86
DTSTART;TZID=Europe/Warsaw:20220114T150000
DTEND;TZID=Europe/Warsaw:20220114T170000
DESCRIPTION:Abstract: Consumer demand for low-power mobile ICs has propelle
 d CMOS scaling to arrive at the fully depleted finFET with foundry offerin
 gs already available at 16/14\, 10\, and 7 nm. The compact three-dimension
 al structure of the finFET offers superior short-channel control that achi
 eves digital power reduction while increasing device performance for a giv
 en area. As system-on-chip technology remains driven by logic and SRAM sca
 ling needs\, designers of analog/mixed-signal subsystems must continue to 
 adapt to new technology constraints. We attempt to summarize the challenge
 s and technology considerations encountered when we port analog/mixed-sign
 al designs to a finFET node. At 16/14 nm and beyond\, designers also face 
 many implications from scaling innovations leading to the finFET such as m
 echanical stressors\, high-K gate dielectric and metal gate\, multiple and
  spacer-based patterning\, and a very complex middle-end-of-line.\n\nCo-sp
 onsored by: Silicon Creations\n\nVirtual: https://events.vtools.ieee.org/m
 /301249
LOCATION:Virtual: https://events.vtools.ieee.org/m/301249
ORGANIZER:kasinski@agh.edu.pl
SEQUENCE:0
SUMMARY:"Nanoscale FinFET Technology for Circuit Designers" Alvin Loke
URL;VALUE=URI:https://events.vtools.ieee.org/m/301249
X-ALT-DESC:Description: <br /><p>Abstract: Consumer demand for low-power mo
 bile ICs has propelled CMOS scaling to arrive at the fully depleted finFET
  with foundry offerings already available at 16/14\, 10\, and 7 nm. The co
 mpact three-dimensional structure of the finFET offers superior short-chan
 nel control that achieves digital power reduction while increasing device 
 performance for a given area. As system-on-chip technology remains driven 
 by logic and SRAM scaling needs\, designers of analog/mixed-signal subsyst
 ems must continue to adapt to new technology constraints. We attempt to su
 mmarize the challenges and technology considerations encountered when we p
 ort analog/mixed-signal designs to a finFET node. At 16/14 nm and beyond\,
  designers also face many implications from scaling innovations leading to
  the finFET such as mechanical stressors\, high-K gate dielectric and meta
 l gate\, multiple and spacer-based patterning\, and a very complex middle-
 end-of-line.</p>
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