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DTSTART:20221106T010000
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DTSTAMP:20220620T175259Z
UID:8FA3D44A-20FB-4653-A572-C78F421300C1
DTSTART;TZID=US/Eastern:20220622T120000
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DESCRIPTION:Power delivery requirements for the early microprocessors were 
 fairly rudimentary due to the relatively low power levels. However\, sever
 al decades of exponential scaling powered by Moore’s law has greatly inc
 reased the power requirements and the complexity of the power delivery sch
 emes. The breakdown in Dennard scaling in the mid-2000s has ushered in the
  multi-core era which has increased the number of cores and the power cons
 umption in microprocessors. The steady growth in the power levels and the 
 number of power rails in high performance microprocessors has increased th
 e power delivery challenges. New trends like heterogeneous integration and
  3D-stacking through advanced packaging technologies further exacerbate th
 e power delivery problem.\n\nIntegrated Voltage Regulators (IVR) have emer
 ged as a key power delivery technology to address these challenges. There 
 are a number of IVR schemes implemented on-die ranging from the simple pow
 er gate to fully integrated switching regulators. The key performance vect
 ors to judge the quality of the IVR are conversion efficiency\, current de
 nsity\, load regulation and configurability. We will look at some of the p
 opular IVR solutions that are being used today and project the performance
  required to keep pace with the expected demand for future microprocessors
 . We will conclude by looking at additional solution vectors such as Power
 Via that are being pursued to address these power delivery challenges.\n\n
 Speaker(s): Kaladhar Radhakrishnan \, \n\nVirtual: https://events.vtools.i
 eee.org/m/306561
LOCATION:Virtual: https://events.vtools.ieee.org/m/306561
ORGANIZER:chanb@binghamton.edu
SEQUENCE:3
SUMMARY:Challenges and Innovations in Power Delivery
URL;VALUE=URI:https://events.vtools.ieee.org/m/306561
X-ALT-DESC:Description: &lt;br /&gt;&lt;p&gt;Power delivery requirements for the early 
 microprocessors were fairly rudimentary due to the relatively low power le
 vels. However\, several decades of exponential scaling powered by Moore&amp;rs
 quo\;s law has greatly increased the power requirements and the complexity
  of the power delivery schemes. The breakdown in Dennard scaling in the mi
 d-2000s has ushered in the multi-core era which has increased the number o
 f cores and the power consumption in microprocessors. The steady growth in
  the power levels and the number of power rails in high performance microp
 rocessors has increased the power delivery challenges.&amp;nbsp\; New trends l
 ike heterogeneous integration and 3D-stacking through advanced packaging t
 echnologies further exacerbate the power delivery problem.&lt;/p&gt;\n&lt;p&gt;Integra
 ted Voltage Regulators (IVR) have emerged as a key power delivery technolo
 gy to address these challenges. There are a number of IVR schemes implemen
 ted on-die ranging from the simple power gate to fully integrated switchin
 g regulators. The key performance vectors to judge the quality of the IVR 
 are conversion efficiency\, current density\, load regulation and configur
 ability. We will look at some of the popular IVR solutions that are being 
 used today and project the performance required to keep pace with the expe
 cted demand for future microprocessors. We will conclude by looking at add
 itional solution vectors such as PowerVia that are being pursued to addres
 s these power delivery challenges.&lt;/p&gt;
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