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DTSTAMP:20220415T221040Z
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DTSTART;TZID=US/Eastern:20220413T130000
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DESCRIPTION:In this lecture semiconductor advanced packaging is defined. Th
 e kinds of advanced packaging are ranked based on their interconnect densi
 ty and electrical performance and are grouped into 2D\, 2.1D\, 2.3D\, 2.5D
 \, and 3D IC integration\, which will be presented and discussed. Key enab
 ling technologies such as flip chip and fan-out will be briefly mentioned.
  The trends and challenges (opportunities) of advanced packaging will be d
 iscussed. Also\, in this lecture\, chiplet design and heterogeneous integr
 ation packaging are defined. The chiplet design and heterogeneous integrat
 ion packaging such as those given by Xilinx\, AMD\, Intel\, TSMC\, and Sam
 sung will be presented and discussed. The lateral communication between ch
 iplets such as the silicon bridges embedded in organic build-up package su
 bstrate and fan-out epoxy molding compound as well as flexible bridges wil
 l be presented. Key enabling technologies such as thermocompression bondin
 g and hybrid bonding will be briefly mentioned. The trends and challenges 
 (opportunities) of chiplet design and heterogeneous integration packaging 
 will be discussed.\n\nSpeaker(s): Dr John Lau\, \n\nVirtual: https://event
 s.vtools.ieee.org/m/311282
LOCATION:Virtual: https://events.vtools.ieee.org/m/311282
ORGANIZER:chanb@binghamton.edu
SEQUENCE:2
SUMMARY:Recent Advances and Trends in Advanced Packaging
URL;VALUE=URI:https://events.vtools.ieee.org/m/311282
X-ALT-DESC:Description: <br /><p>In this lecture semiconductor advanced pac
 kaging is defined. The kinds of advanced packaging are ranked based on the
 ir interconnect density and electrical performance and are grouped into 2D
 \, 2.1D\, 2.3D\, 2.5D\, and 3D IC integration\, which will be presented an
 d discussed. Key enabling technologies such as flip chip and fan-out will 
 be briefly mentioned. The trends and challenges (opportunities) of advance
 d packaging will be discussed. Also\, in this lecture\, chiplet design and
  heterogeneous integration packaging are defined. The chiplet design and h
 eterogeneous integration packaging such as those given by Xilinx\, AMD\, I
 ntel\, TSMC\, and Samsung will be presented and discussed. The lateral com
 munication between chiplets such as the silicon bridges embedded in organi
 c build-up package substrate and fan-out epoxy molding compound as well as
  flexible bridges will be presented. Key enabling technologies such as the
 rmocompression bonding and hybrid bonding will be briefly mentioned. The t
 rends and challenges (opportunities) of chiplet design and heterogeneous i
 ntegration packaging will be discussed.</p>
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