BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Europe/Warsaw BEGIN:DAYLIGHT DTSTART:20220327T030000 TZOFFSETFROM:+0100 TZOFFSETTO:+0200 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=3 TZNAME:CEST END:DAYLIGHT BEGIN:STANDARD DTSTART:20221030T020000 TZOFFSETFROM:+0200 TZOFFSETTO:+0100 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=10 TZNAME:CET END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20220523T092158Z UID:42E24020-1F9D-4905-B6E6-2B5D36D902B8 DTSTART;TZID=Europe/Warsaw:20220512T093000 DTEND;TZID=Europe/Warsaw:20220512T123000 DESCRIPTION:Abstract– Over the past three decades\, the demand of communi cation makes different kinds of standards evolute exponentially in speed. Along with the higher and higher wireline data rates\, more impairments in the SerDes system and circuitry may reasonably change the link architectu re in an evolution. For example\, the impairments\, such as an inter-symbo l interference\, ISI (due to frequency dependent attenuation)\, crosstalk\ , reflection\, noise\, jitter\, linearity\, device mismatch\, capacitive o r inductive parasitic\, power/ground integrity\, etc.\, could not be a con cern at old generation SerDes\, but could be an issue at a high-speed SerD es system and requires a different architecture to mitigate the impairment s.\nThis presentation will begin with providing an introduction of a wirel ine serial link\, including a few impairments. Then move forward with rear chitecting the SerDes topology to mitigate those impairments. The correspo nding SerDes system and circuit design techniques would be explored during the iterations between those impairments and rearchitecting process. Fina lly\, the generic high-speed Serdes architecture with some circuit images will be reviewed and discussed. A further Q&A discussion will be performed in the end of this presentation as well.\n\nCo-sponsored by: Silicon Crea tions Poland\n\nSpeaker(s): Chung-Chun Chen (CC)\, \n\nRoom: 121\, Bldg: B 1\, AGH University of Science and Technology\, Av. Mickiewicza 30\, Krakó w\, Malopolskie\, Poland\, 30-059 LOCATION:Room: 121\, Bldg: B1\, AGH University of Science and Technology\, Av. Mickiewicza 30\, Kraków\, Malopolskie\, Poland\, 30-059 ORGANIZER:krzysztof.kasinski@siliconcr.com SEQUENCE:7 SUMMARY:SerDes Architecture from Impairments (On-Site) URL;VALUE=URI:https://events.vtools.ieee.org/m/313824 X-ALT-DESC:Description: <br /><p><strong><span data-contrast="none">Abstrac t&ndash\;</span></strong><span data-contrast="none"> Over the past three d ecades\, the demand of communication makes different kinds of standards ev olute exponentially in speed. Along with the higher and higher wireline da ta rates\, more impairments in the SerDes system and circuitry may reasona bly change the link architecture in an evolution. For example\, the impair ments\, such as an inter-symbol interference\, ISI (due to frequency depen dent attenuation)\, crosstalk\, reflection\, noise\, jitter\, linearity\, device mismatch\, capacitive or inductive parasitic\, power/ground integri ty\, etc.\, could not be a concern at old generation SerDes\, but could be an issue at a high-speed SerDes system and requires a different architect ure to mitigate the impairments.</span>&nbsp\;<br /><span data-contrast="n one">This presentation will begin with providing an introduction of a wire line serial link\, including a few impairments. Then move forward with rea rchitecting the SerDes topology to mitigate those impairments. The corresp onding SerDes system and circuit design techniques would be explored durin g the iterations between those impairments and rearchitecting process. Fin ally\, the generic </span><span data-contrast="auto">high-speed </span><sp an data-contrast="auto">Serdes architecture with some circuit images</span ><span data-contrast="none"> will be reviewed and discussed. A further Q&a mp\;A discussion will be performed in the end of this presentation as well .</span><span data-ccp-props="{&quot\;201341983&quot\;:0\,&quot\;335559739 &quot\;:0\,&quot\;335559740&quot\;:240}">&nbsp\;</span></p> END:VEVENT END:VCALENDAR