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DTSTAMP:20220608T155615Z
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DESCRIPTION:Most of the existing circuit design methodologies are based on 
 iterative methods\, which are very time consuming and sometimes far from b
 eing optimal. The process of analog circuit design is generally so complex
  that most designers rely mainly on their own intuition to design and move
  toward an acceptable design point\, which in many cases is based on a lon
 g process of trial-and-errors. There are two dominant circuit design metho
 dologies used in academic institutions and industry: (1) Inversion-Coeffic
 ient (IC) method\, and (2) Gm/IDS (GmID) approach. While IC method is more
  analytical\, GmID require extensive device characterizations in order to 
 create a comprehensive data-base describing device behavior in all modes o
 f operations for different device sizes. Meanwhile\, designers need to dev
 elop their own optimization scripts to search through all possible design 
 points and select the best fit for their application\, as these methodolog
 ies are not supported by the common EDA Tools.\n\nIn this seminar\, an imp
 roved design methodology will be introduced\, which lies somewhere between
  the two approaches. Called C/IDS\, the proposed design methodology requir
 es prior knowledge on only few technology-dependent parameters\, which are
  very easy to extract. Due to its analytical nature\, this approach provid
 es comprehensive design insight\, while the flow of design can be automati
 zed easily. Several examples will be provided to show effectiveness of the
  proposed algorithm for implementing energy and power efficient circuits. 
 A set of data points demonstrating how performance of analog circuits evol
 ve with technology scaling will be provided.\n\nSpeaker(s): Armin Tajalli\
 , \n\nVirtual: https://events.vtools.ieee.org/m/314527
LOCATION:Virtual: https://events.vtools.ieee.org/m/314527
ORGANIZER:wagih.ismail@ieee.org
SEQUENCE:6
SUMMARY:C/ID: A Design Methodology for Implementing Nanoscale Analog FET Ci
 rcuits.
URL;VALUE=URI:https://events.vtools.ieee.org/m/314527
X-ALT-DESC:Description: <br /><p>Most of the existing circuit design method
 ologies are based on iterative methods\, which are very time consuming and
  sometimes far from being optimal. The process of analog circuit design is
  generally so complex that most designers rely mainly on their own intuiti
 on to design and move toward an acceptable design point\, which in many ca
 ses is based on a long process of trial-and-errors. There are two dominant
  circuit design methodologies used in academic institutions and industry: 
 (1) Inversion-Coefficient (IC) method\, and (2) Gm/IDS (GmID) approach. Wh
 ile IC method is more analytical\, GmID require extensive device character
 izations in order to create a comprehensive data-base describing device be
 havior in all modes of operations for different device sizes. Meanwhile\, 
 designers need to develop their own optimization scripts to search through
  all possible design points and select the best fit for their application\
 , as these methodologies are not supported by the common EDA Tools.</p>\n<
 p>In this seminar\, an improved design methodology will be introduced\, wh
 ich lies somewhere between the two approaches. Called C/IDS\, the proposed
  design methodology requires prior knowledge on only few technology-depend
 ent parameters\, which are very easy to extract. Due to its analytical nat
 ure\, this approach provides comprehensive design insight\, while the flow
  of design can be automatized easily. Several examples will be provided to
  show effectiveness of the proposed algorithm for implementing energy and 
 power efficient circuits. A set of data points demonstrating how performan
 ce of analog circuits evolve with technology scaling will be provided. &nb
 sp\;</p>
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