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DTSTART:20221106T010000
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DTSTAMP:20220622T183012Z
UID:7F7B2DE8-80B9-4822-99A9-CDA76461ED63
DTSTART;TZID=America/Los_Angeles:20220622T090000
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DESCRIPTION:Power delivery requirements for the early microprocessors were 
 fairly rudimentary due to the relatively low power levels. However\, sever
 al decades of exponential scaling powered by Moore’s law has greatly inc
 reased the power requirements and the complexity of the power delivery sch
 emes. The breakdown in Dennard scaling in the mid-2000s has ushered in the
  multi-core era which has increased the number of cores and the power cons
 umption in microprocessors. The steady growth in the power levels and the 
 number of power rails in high performance microprocessors has increased th
 e power delivery challenges. New trends like heterogeneous integration and
  3D-stacking through advanced packaging technologies further exacerbate th
 e power delivery problem. Integrated Voltage Regulators (IVR) have emerged
  as a key power delivery technology to address these challenges. There are
  a number of IVR schemes implemented on-die ranging from the simple power 
 gate to fully integrated switching regulators. The key performance vectors
  to judge the quality of the IVR are conversion efficiency\, current densi
 ty\, load regulation and configurability. We will look at some of the popu
 lar IVR solutions that are being used today and project the performance re
 quired to keep pace with the expected demand for future microprocessors. W
 e will conclude by looking at additional solution vectors such as PowerVia
  that are being pursued to address these power delivery challenges.\n\nSpe
 aker(s): Kaladhar Radhakrishnan\, \n\nVirtual: https://events.vtools.ieee.
 org/m/315445
LOCATION:Virtual: https://events.vtools.ieee.org/m/315445
ORGANIZER:p.wesling@ieee.org
SEQUENCE:1
SUMMARY:System-In-Package Power Delivery: Challenges And Innovations
URL;VALUE=URI:https://events.vtools.ieee.org/m/315445
X-ALT-DESC:Description: &lt;br /&gt;&lt;p&gt;Power delivery requirements for the early 
 microprocessors were fairly rudimentary due to the relatively low power le
 vels. However\, several decades of exponential scaling powered by Moore&amp;rs
 quo\;s law has greatly increased the power requirements and the complexity
  of the power delivery schemes. The breakdown in Dennard scaling in the mi
 d-2000s has ushered in the multi-core era which has increased the number o
 f cores and the power consumption in microprocessors. The steady growth in
  the power levels and the number of power rails in high performance microp
 rocessors has increased the power delivery challenges. New trends like het
 erogeneous integration and 3D-stacking through advanced packaging technolo
 gies further exacerbate the power delivery problem. &lt;strong&gt;Integrated Vol
 tage Regulators (IVR) &lt;/strong&gt;have emerged as a key power delivery techno
 logy to address these challenges. There are a number of IVR schemes implem
 ented on-die ranging from the simple power gate to fully integrated switch
 ing regulators. The key performance vectors to judge the quality of the IV
 R are conversion efficiency\, current density\, load regulation and config
 urability. We will look at some of the popular IVR solutions that are bein
 g used today and project the performance required to keep pace with the ex
 pected demand for future microprocessors. We will conclude by looking at a
 dditional solution vectors such as PowerVia that are being pursued to addr
 ess these power delivery challenges.&lt;/p&gt;
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