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DESCRIPTION:Neuromorphic and AI computing hardware is trending away from tr
 aditional von Neumann computational architectures. This transition is open
 ing the door to a wide range of novel devices and integration solutions. O
 ver the past 10 years\, my research group has focused on fabrication and i
 ntegration strategies for CMOS-compatible\, non-volatile\, memory devices 
 (aka: memristors). These memristive devices have the potential to act as n
 euronal synapses in neural networks\, but can also function as tunable ele
 ments in array-based accelerators. Introducing unique materials and novel 
 memristive devices into the traditional CMOS fabrication process presents 
 many challenges\, from both the process integration and packaging standpoi
 nt. In this presentation I will discuss integration strategies that we hav
 e used to develop novel hardware solutions and translation of laboratory-s
 cale demonstrations towards integration on 300mm wafer platforms utilizing
  the Albany Nanotech 300mm foundry.\n\nSpeaker(s): Dr. Nate Cady\, \n\nBld
 g: CNSE\, CESTM Audirotium\, Albany\, New York\, United States\, Virtual: 
 https://events.vtools.ieee.org/m/316254
LOCATION:Bldg: CNSE\, CESTM Audirotium\, Albany\, New York\, United States\
 , Virtual: https://events.vtools.ieee.org/m/316254
ORGANIZER:sagarika.mukesh@gmail.com
SEQUENCE:2
SUMMARY:Development and Integration Strategies for Non-volatile Resistive M
 emory in the Context of Neuromorphic Computing and AI Hardware
URL;VALUE=URI:https://events.vtools.ieee.org/m/316254
X-ALT-DESC:Description: <br /><p>Neuromorphic and AI computing hardware is 
 trending away from traditional von Neumann computational architectures. Th
 is transition is opening the door to a wide range of novel devices and int
 egration solutions. Over the past 10 years\, my research group has focused
  on fabrication and integration strategies for CMOS-compatible\, non-volat
 ile\, memory devices (aka: memristors). These memristive devices have the 
 potential to act as neuronal synapses in neural networks\, but can also fu
 nction as tunable elements in array-based accelerators. Introducing unique
  materials and novel memristive devices into the traditional CMOS fabricat
 ion process presents many challenges\, from both the process integration a
 nd packaging standpoint. In this presentation I will discuss integration s
 trategies that we have used to develop novel hardware solutions and transl
 ation of laboratory-scale demonstrations towards integration on 300mm wafe
 r platforms utilizing the Albany Nanotech 300mm foundry.</p>
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