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DTSTART:20221002T030000
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DTSTAMP:20220630T095900Z
UID:2C1C504F-E9EC-4D91-99C7-BC2B919AA810
DTSTART;TZID=Australia/Adelaide:20220627T193000
DTEND;TZID=Australia/Adelaide:20220627T203000
DESCRIPTION:Dear IEEE members and guests\,\n\nThe next IEEE Control\, Aeros
 pace and Electronic Systems (CAES) seminar will be on Monday\, 27th June\,
  2022 at 7:30 pm (Adelaide time).\n\nThe speaker is Dr C. J. Kikkert BE (H
 ons I)\, PhD\, FIEAust\, LSMIEEE\, CPEng\, he will be presenting a seminar
  on:\n\nA Phasor Measurement Unit (PMU) Algorithm for FPGA implementation\
 n\nPlease aim to join the WebEx meeting beforehand\, so we can start on ti
 me.\n\nhttps://ieeemeetings.webex.com/ieeemeetings/j.php?MTID=m7aa7e54b1fe
 8edc8186f7a04920ed965\n\nWebinar number (access code): 2538 375 4438\n\nAl
 so\, please check out the IEEE SA Section website: https://r10.ieee.org/sa
 us/\n\nRegards\n\nWaddah Al-Ashwal\n\nIEEE SA CAES Chapter Chair\n\nA Phas
 or Measurement Unit (PMU) Algorithm for FPGA implementation\n\nPhasor Meas
 urement Units are used to measure Voltage\, Phase\, Frequency and Rate of 
 Change of Frequency. A Voltage Phasor accuracy better the 1% and frequency
  error of less than 5mHz (0.01%) and must be obtained within 2 mains cycle
 s time. To ensure high measurement availability and reliability\, an FPGA 
 implementation of the PMU is being implemented. The seminar will describe 
 the PMU algorithm\, which includes IQ demodulation\, phasor conversion and
  filtering of the mains waveform. The seminar will discuss the Digital Sig
 nal Processes (DSP) choices required to ensure a minimum time delay FPGA i
 mplementation\, whilst achieving the required measurement accuracy.\n\nSpe
 aker(s): Dr Keith Kikkert\, \n\nVirtual: https://events.vtools.ieee.org/m/
 316276
LOCATION:Virtual: https://events.vtools.ieee.org/m/316276
ORGANIZER:waashwal@ieee.org
SEQUENCE:5
SUMMARY:A Phasor Measurement Unit (PMU) Algorithm for FPGA implementation
URL;VALUE=URI:https://events.vtools.ieee.org/m/316276
X-ALT-DESC:Description: &lt;br /&gt;&lt;p style=&quot;margin-bottom: 0cm\; background: tr
 ansparent\;&quot;&gt;&lt;span style=&quot;color: #0e101a\;&quot;&gt;&lt;span style=&quot;background: trans
 parent\;&quot;&gt;Dear IEEE members and guests\,&lt;/span&gt;&lt;/span&gt;&lt;/p&gt;\n&lt;p style=&quot;marg
 in-bottom: 0cm\; background: transparent\;&quot;&gt;&lt;span style=&quot;color: #0e101a\;&quot;
 &gt;&lt;span style=&quot;background: transparent\;&quot;&gt;The next IEEE Control\, Aerospace
  and Electronic Systems (CAES) seminar will be on Monday\, 2&lt;/span&gt;&lt;/span&gt;
 &lt;span style=&quot;color: #0e101a\;&quot;&gt;&lt;span style=&quot;background: transparent\;&quot;&gt;7&lt;/
 span&gt;&lt;/span&gt;&lt;span style=&quot;color: #0e101a\;&quot;&gt;&lt;sup&gt;&lt;span style=&quot;background: t
 ransparent\;&quot;&gt;t&lt;/span&gt;&lt;/sup&gt;&lt;/span&gt;&lt;span style=&quot;color: #0e101a\;&quot;&gt;&lt;sup&gt;&lt;sp
 an style=&quot;background: transparent\;&quot;&gt;h&lt;/span&gt;&lt;/sup&gt;&lt;/span&gt;&lt;span style=&quot;col
 or: #0e101a\;&quot;&gt;&lt;span style=&quot;background: transparent\;&quot;&gt; &lt;/span&gt;&lt;/span&gt;&lt;spa
 n style=&quot;color: #0e101a\;&quot;&gt;&lt;span style=&quot;background: transparent\;&quot;&gt;June&lt;/s
 pan&gt;&lt;/span&gt;&lt;span style=&quot;color: #0e101a\;&quot;&gt;&lt;span style=&quot;background: transpa
 rent\;&quot;&gt;\, 202&lt;/span&gt;&lt;/span&gt;&lt;span style=&quot;color: #0e101a\;&quot;&gt;&lt;span style=&quot;ba
 ckground: transparent\;&quot;&gt;2&lt;/span&gt;&lt;/span&gt;&lt;span style=&quot;color: #0e101a\;&quot;&gt;&lt;sp
 an style=&quot;background: transparent\;&quot;&gt; at 7:30 pm (Adelaide time).&lt;/span&gt;&lt;/
 span&gt;&lt;/p&gt;\n&lt;p style=&quot;margin-bottom: 0cm\; background: transparent\;&quot;&gt;&lt;span
  style=&quot;color: #0e101a\;&quot;&gt;&lt;span style=&quot;background: transparent\;&quot;&gt;The spea
 ker is Dr C. J. Kikkert BE (Hons I)\, PhD\, FIEAust\, LSMIEEE\, CPEng\, he
  will be presenting a seminar on:&lt;/span&gt;&lt;/span&gt;&lt;/p&gt;\n&lt;p style=&quot;margin-bott
 om: 0cm\; background: transparent\;&quot;&gt;&lt;strong&gt;&lt;span style=&quot;color: #0e101a\;
 &quot;&gt;&lt;span style=&quot;background: transparent\;&quot;&gt;A Phasor Measurement Unit (PMU) 
 Algorithm for FPGA implementation&lt;/span&gt;&lt;/span&gt;&lt;/strong&gt;&lt;span style=&quot;color
 : #0e101a\;&quot;&gt;&lt;span style=&quot;background: transparent\;&quot;&gt;&amp;nbsp\;&lt;/span&gt;&lt;/span&gt;
 &lt;/p&gt;\n&lt;p&gt;Please aim to join the WebEx meeting beforehand\, so we can start
  on time.&lt;/p&gt;\n&lt;p&gt;&lt;a href=&quot;https://ieeemeetings.webex.com/ieeemeetings/j.p
 hp?MTID=m7aa7e54b1fe8edc8186f7a04920ed965&quot;&gt;https://ieeemeetings.webex.com/
 ieeemeetings/j.php?MTID=m7aa7e54b1fe8edc8186f7a04920ed965&lt;/a&gt;&lt;/p&gt;\n&lt;p&gt;Webi
 nar number (access code): 2538 375 4438&lt;/p&gt;\n&lt;p style=&quot;margin-bottom: 0cm\
 ; background: transparent\;&quot;&gt;&lt;span style=&quot;color: #0e101a\;&quot;&gt;&lt;span style=&quot;b
 ackground: transparent\;&quot;&gt;Also\, please check out the IEEE SA Section webs
 ite: &lt;/span&gt;&lt;/span&gt;&lt;a href=&quot;https://r10.ieee.org/saus/&quot; target=&quot;_blank&quot; re
 l=&quot;noopener&quot;&gt;&lt;span style=&quot;color: #0000ff\;&quot;&gt;&lt;span style=&quot;background: trans
 parent\;&quot;&gt;https://r10.ieee.org/saus/&lt;/span&gt;&lt;/span&gt;&lt;/a&gt;&lt;/p&gt;\n&lt;p style=&quot;marg
 in-bottom: 0cm\; background: transparent\;&quot;&gt;&lt;span style=&quot;color: #0e101a\;&quot;
 &gt;&lt;span style=&quot;background: transparent\;&quot;&gt;Regards&lt;/span&gt;&lt;/span&gt;&lt;/p&gt;\n&lt;p sty
 le=&quot;margin-bottom: 0cm\; background: transparent\;&quot;&gt;&lt;span style=&quot;color: #0
 e101a\;&quot;&gt;&lt;span style=&quot;background: transparent\;&quot;&gt;Waddah Al-Ashwal&lt;/span&gt;&lt;/
 span&gt;&lt;/p&gt;\n&lt;p style=&quot;margin-bottom: 0cm\; background: transparent\;&quot;&gt;&lt;span
  style=&quot;color: #0e101a\;&quot;&gt;&lt;span style=&quot;background: transparent\;&quot;&gt;IEEE SA 
 CAES Chapter Chair&lt;/span&gt;&lt;/span&gt;&lt;/p&gt;\n&lt;p style=&quot;margin-bottom: 0cm\; backg
 round: transparent\;&quot;&gt;&amp;nbsp\;&lt;/p&gt;\n&lt;p style=&quot;margin-bottom: 0cm\; line-hei
 ght: 100%\;&quot;&gt;&lt;strong&gt;&lt;span style=&quot;color: #0e101a\;&quot;&gt;&lt;span style=&quot;backgroun
 d: transparent\;&quot;&gt;A Phasor Measurement Unit (PMU) Algorithm for FPGA imple
 mentation&lt;/span&gt;&lt;/span&gt;&lt;/strong&gt;&lt;span style=&quot;color: #0e101a\;&quot;&gt;&lt;span style
 =&quot;background: transparent\;&quot;&gt;&amp;nbsp\;&lt;/span&gt;&lt;/span&gt;&lt;/p&gt;\n&lt;p&gt;Phasor Measurem
 ent Units are used to measure Voltage\, Phase\, Frequency and Rate of Chan
 ge of Frequency. A Voltage Phasor accuracy better the 1% and frequency err
 or of less than 5mHz (0.01%) and must be obtained within 2 mains cycles ti
 me. To ensure high measurement availability and reliability\, an FPGA impl
 ementation of the PMU is being implemented. The seminar will describe the 
 PMU algorithm\, which includes IQ demodulation\, phasor conversion and fil
 tering of the mains waveform. The seminar will discuss the Digital Signal 
 Processes (DSP) choices required to ensure a minimum time delay FPGA imple
 mentation\, whilst achieving the required measurement accuracy.&lt;/p&gt;
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