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DTSTAMP:20220705T100408Z
UID:33202A0B-D496-412F-9289-DF0AFCF45F61
DTSTART;TZID=America/New_York:20220628T100000
DTEND;TZID=America/New_York:20220628T113000
DESCRIPTION:Dr. Sudip Shekhar from the University of British Columbia will 
 give an in-person talk\, the abstract of which is below:\n\nAbstract:\nDig
 ital accelerators in the latest generation of CMOS processes support multi
 ply\, and accumulate (MAC) operations at energy efficiencies spanning 10
 –100 fJ/Op. However\, the operating speed for such MAC operations is oft
 en limited to a few hundreds of MHz. Optical or optoelectronic MAC operati
 ons on today’s silicon photonic IC platforms can be realized at a speed 
 of tens of GHz\, leading to much lower latency and higher throughput. In t
 his talk\, I will describe the integrated silicon photonic MAC circuits ba
 sed on Mach–Zehnder and microring structures. I will present the bounds 
 on energy efficiency and scaling limits for N × N MAC networks based on t
 he optical and electrical link budget\, as well as some packaging concerns
  related to the CMOS/photonic co-integration. I will also describe researc
 h directions that can overcome the current limitations.\n\nSpeaker(s): Dr.
  Sudip Shekhar\, \n\nRoom: 1.162\, Bldg: EV\, 1515 Ste-Catherine West\, Mo
 ntreal\, Quebec\, Canada\, H3G 1M8
LOCATION:Room: 1.162\, Bldg: EV\, 1515 Ste-Catherine West\, Montreal\, Queb
 ec\, Canada\, H3G 1M8
ORGANIZER:gcowan@ece.concordia.ca
SEQUENCE:5
SUMMARY:IEEE SSCS DL Talk: Scaling up silicon photonic-based accelerators: 
 Challenges and opportunities
URL;VALUE=URI:https://events.vtools.ieee.org/m/317277
X-ALT-DESC:Description: <br /><p>Dr. Sudip Shekhar from the University of B
 ritish Columbia will give an in-person talk\, the abstract of which is bel
 ow:</p>\n<p><strong>Abstract:</strong></p>\n<div><span lang="EN-US">Digita
 l accelerators in the latest generation of CMOS processes support multiply
 \, and accumulate (MAC) operations at energy efficiencies spanning 10&ndas
 h\;100 fJ/Op. However\, the operating speed for such MAC operations is oft
 en limited to a few hundreds of MHz. Optical or optoelectronic MAC operati
 ons on today&rsquo\;s silicon photonic IC platforms can be realized at a s
 peed of tens of GHz\, leading to much lower latency and higher throughput.
  In this talk\, I will describe the integrated silicon photonic MAC circui
 ts based on Mach&ndash\;Zehnder and microring structures. I will present t
 he bounds on energy efficiency and scaling limits for N &times\; N MAC net
 works based on the optical and electrical link budget\, as well as some pa
 ckaging concerns related to the CMOS/photonic co-integration. I will also 
 describe research directions that can overcome the current limitations.</s
 pan></div>\n<p>&nbsp\;</p>
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