BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Europe/Warsaw BEGIN:DAYLIGHT DTSTART:20220327T030000 TZOFFSETFROM:+0100 TZOFFSETTO:+0200 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=3 TZNAME:CEST END:DAYLIGHT BEGIN:STANDARD DTSTART:20221030T020000 TZOFFSETFROM:+0200 TZOFFSETTO:+0100 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=10 TZNAME:CET END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20220711T090212Z UID:872D7285-CDA9-4C81-9FCE-B17436EF1AFA DTSTART;TZID=Europe/Warsaw:20220708T110000 DTEND;TZID=Europe/Warsaw:20220708T130000 DESCRIPTION:Abstract: What is a good frequency synthesizer? A survey of CMO S phase-locked loops (PLLs) over the last two decades shows that the overa ll performance of PLL-based frequency synthesizers is bounded by a tradeof f between noise\, area\, and power consumption. Analog PLLs with a charge- pump integrator (Type-II) suffer from charge-pump and detector noise\, and are area- and power-hungry. All-digital PLLs are compact and friendly to technology scaling but limited in noise performance under a restrained pow er budget.\nThe simplest frequency synthesizer is one utilizing the least noise-inducing components in the loop. The recipe to design the lowest noi se synthesizer is simple: (1) Choose the VCO with the lowest phase noise. (2) Reduce its low-offset phase noise by locking it to the cleanest freque ncy reference with a large loop bandwidth. (3) Eliminate/suppress other no ise sources. Such a loop can be realized as Type-I\, without an integrator in the loop filter. Such synthesizers thus comprise subsampling Type-I PL Ls and injection-locked (Type-I) PLLs. They achieve low noise performance in a compact footprint and low power budget. And the limitations of classi cal Type-I\, subsampling\, and injection-locked topologies can be remedied using two classical design philosophies - 1) a simple design is often a g ood design\, and 2) use digital CMOS where it is good at. Such digitally-a ssisted analog synthesizers include the best of both worlds.\n\nRoom: H24\ , Bldg: B1\, Av. Mickiewcza 30\, Krakow\, Malopolskie\, Poland\, Virtual: https://events.vtools.ieee.org/m/319072 LOCATION:Room: H24\, Bldg: B1\, Av. Mickiewcza 30\, Krakow\, Malopolskie\, Poland\, Virtual: https://events.vtools.ieee.org/m/319072 ORGANIZER:krzysztof.kasinski@siliconcr.com SEQUENCE:3 SUMMARY:Frequency Synthesis Type One - Sudip Shekhar (SSCS Chapter Poland) URL;VALUE=URI:https://events.vtools.ieee.org/m/319072 X-ALT-DESC:Description: <br /><div dir="auto">Abstract: What is a good freq uency synthesizer? A survey of CMOS phase-locked loops (PLLs) over the las t two decades shows that the overall performance of PLL-based frequency sy nthesizers is bounded by a tradeoff between noise\, area\, and power consu mption. Analog PLLs with a charge-pump integrator (Type-II) suffer from ch arge-pump and detector noise\, and are area- and power-hungry. All-digital PLLs are compact and friendly to technology scaling but limited in noise performance under a restrained power budget.</div>\n<div dir="auto">The si mplest frequency synthesizer is one utilizing the least noise-inducing com ponents in the loop. The recipe to design the lowest noise synthesizer is simple: (1) Choose the VCO with the lowest phase noise. (2) Reduce its low -offset phase noise by locking it to the cleanest frequency reference with a large loop bandwidth. (3) Eliminate/suppress other noise sources. Such a loop can be realized as Type-I\, without an integrator in the loop filte r. Such synthesizers thus comprise subsampling Type-I PLLs and injection-l ocked (Type-I) PLLs. They achieve low noise performance in a compact footp rint and low power budget. And the limitations of classical Type-I\, subsa mpling\, and injection-locked topologies can be remedied using two classic al design philosophies - 1) a simple design is often a good design\, and 2 ) use digital CMOS where it is good at. Such digitally-assisted analog syn thesizers include the best of both worlds.</div> END:VEVENT END:VCALENDAR