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DTSTAMP:20220911T231118Z
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DTSTART;TZID=America/Los_Angeles:20220825T170000
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DESCRIPTION:In this lecture\, advanced packaging is defined. The kinds of a
 dvanced packaging are ranked based on their interconnect density and elect
 rical performance\, and are grouped into 2-D\, 2.1-D\, 2.3-D\, 2.5-D\, and
  3-D IC integration\, which will be presented and discussed. Chiplet desig
 n and heterogeneous integration packaging provide alternatives to the syst
 em on chips (especially for advanced nodes) will be discussed. The lateral
  communication between chiplets\, such as the silicon bridges embedded in 
 organic build-up package substrate and fan-out epoxy molding compound\, as
  well as flexible bridges\, will be presented. The UCIe (Universal Chiplet
  Interconnect Express) will also be briefly mentioned. Different substrate
 s\, such as size\, pin-count\, and metal linewidth and spacing for heterog
 eneous integration packaging\, are examined. Fan-out packaging\, such as t
 he chip-first with die face-up\, chip-first with die face-down\, and chip-
 last and their difference\, will be provided. Flip-chip assembly by mass r
 eflow\, thermocompression bonding\, and bumpless hybrid bonding will be br
 iefly mentioned first.\n\nSpeaker(s): Dr. John Lau\, \n\nAZ Auditorium\, 1
 0155 Pacific Heights Blvd\, San Diego\, California\, United States\, 92121
LOCATION:AZ Auditorium\, 10155 Pacific Heights Blvd\, San Diego\, Californi
 a\, United States\, 92121
ORGANIZER:pthadesar@ieee.org
SEQUENCE:7
SUMMARY:Recent Advances and Trends in Advanced Packaging
URL;VALUE=URI:https://events.vtools.ieee.org/m/321650
X-ALT-DESC:Description: <br /><p>In this lecture\, advanced packaging is de
 fined. The kinds of advanced packaging are ranked based on their interconn
 ect density and electrical performance\, and are grouped into 2-D\, 2.1-D\
 , 2.3-D\, 2.5-D\, and 3-D IC integration\, which will be presented and dis
 cussed. Chiplet design and heterogeneous integration packaging provide alt
 ernatives to the system on chips (especially for advanced nodes) will be d
 iscussed. The lateral communication between chiplets\, such as the silicon
  bridges embedded in organic build-up package substrate and fan-out epoxy 
 molding compound\, as well as flexible bridges\, will be presented. The UC
 Ie (Universal Chiplet Interconnect Express) will also be briefly mentioned
 . Different substrates\, such as size\, pin-count\, and metal linewidth an
 d spacing for heterogeneous integration packaging\, are examined. Fan-out 
 packaging\, such as the chip-first with die face-up\, chip-first with die 
 face-down\, and chip-last and their difference\, will be provided. Flip-ch
 ip assembly by mass reflow\, thermocompression bonding\, and bumpless hybr
 id bonding will be briefly mentioned first.</p>
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