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DTSTAMP:20221123T030637Z
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DTSTART;TZID=America/New_York:20220919T180000
DTEND;TZID=America/New_York:20220919T193000
DESCRIPTION:The presentation starts with an introduction to memory systems 
 in computing devices such as computers\, tablets or smartphones. Then\, an
  in-depth analysis of standard memory systems for low-power and high-perfo
 rmance applications is provided. The interactions between the signaling\, 
 clocking architecture and packaging technology of a memory interface as we
 ll as how these interactions determine the achievable data rates and power
  efficiency are discussed. Signaling and clocking schemes for standard mem
 ories\, including DDR3 and DDR4 (DDR5)\, and mobile memories\, such as LPD
 DR3 and LPPDR4 (LPDDR5) are detailed and compared against each other. The 
 emerging 2.5D/3D memory systems such as HBM1/2/2E\, and HMC1/2 and beyond 
 are also presented. Packaging options such as BGA\, PoP\, and the emerging
  2.5D/3D are also discussed. To analyze and compare different state-of-the
 -art memory interfaces\, the following metrics are used in the analysis: c
 ost\, power efficiency\, bandwidth\, design complexity\, signal and power 
 integrity\, thermal solution\, and form factor. The audience will gain an 
 in-depth understanding of high-speed memory interfaces\; learn about the i
 nteractions between the signaling\, clocking architecture and packaging te
 chnology of a memory interface\, and find out how those interactions deter
 mine the achievable data rates and power efficiency. The presentation will
  conclude by demonstrating how this knowledge can be used to analyze and c
 ompare different state-of-the-art memory interfaces to help attendees impl
 ement or select a solution which best fits their specific application.\n\n
 Co-sponsored by: STARaCom\n\nSpeaker(s): Dr. Wendem Beyene\, \n\nRoom: 603
 \, Bldg: McConnell Eng. Building \, McGill University\, 3480 University St
 \, Montreal\, Quebec\, Canada\, H3A0E9\, Virtual: https://events.vtools.ie
 ee.org/m/324273
LOCATION:Room: 603\, Bldg: McConnell Eng. Building \, McGill University\, 3
 480 University St\, Montreal\, Quebec\, Canada\, H3A0E9\, Virtual: https:/
 /events.vtools.ieee.org/m/324273
ORGANIZER:roni.khazaka@mcgill.ca
SEQUENCE:6
SUMMARY:Design and SI/PI Analysis of High-Performance Memory Systems
URL;VALUE=URI:https://events.vtools.ieee.org/m/324273
X-ALT-DESC:Description: <br /><p>The presentation starts with an introducti
 on to memory systems in computing devices such as computers\, tablets or s
 martphones. Then\, an in-depth analysis of standard memory systems for low
 -power and high-performance applications is provided. The interactions bet
 ween the signaling\, clocking architecture and packaging technology of a m
 emory interface as well as how these interactions determine the achievable
  data rates and power efficiency are discussed. Signaling and clocking sch
 emes for standard memories\, including DDR3 and DDR4 (DDR5)\, and mobile m
 emories\, such as LPDDR3 and LPPDR4 (LPDDR5) are detailed and compared aga
 inst each other. The emerging 2.5D/3D memory systems such as HBM1/2/2E\, a
 nd HMC1/2 and beyond are also presented. Packaging options such as BGA\, P
 oP\, and the emerging 2.5D/3D are also discussed. To analyze and compare d
 ifferent state-of-the-art memory interfaces\, the following metrics are us
 ed in the analysis: cost\, power efficiency\, bandwidth\, design complexit
 y\, signal and power integrity\, thermal solution\, and form factor. The a
 udience will gain an in-depth understanding of high-speed memory interface
 s\; learn about the interactions between the signaling\, clocking architec
 ture and packaging technology of a memory interface\, and find out how tho
 se interactions determine the achievable data rates and power efficiency. 
 The presentation will conclude by demonstrating how this knowledge can be 
 used to analyze and compare different state-of-the-art memory interfaces t
 o help attendees implement or select a solution which best fits their spec
 ific application.</p>
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