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DTSTART:20230312T030000
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DTSTART:20221106T010000
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DTSTAMP:20221125T141705Z
UID:A5793244-BD9E-4AA2-9233-49DDDC20F4EF
DTSTART;TZID=America/Denver:20221118T100000
DTEND;TZID=America/Denver:20221118T110000
DESCRIPTION:High performance fractional-N phase-locked loops (PLLs) are ess
 ential elements of any advanced electronic systems. In recent years\, both
  analog and all-digital PLLs employing sampling or sub-sampling phase dete
 ctor have gained popularity and demonstrated below 100-fs integrated jitte
 r and superior figure-of-merit. This talk focuses on this PLL architecture
  and elaborates the advanced design techniques to achieve low jitter\, low
  fractional spurs\, fast locking\, and low power operation. Both circuits 
 design and digital calibration techniques will be presented in detail. In 
 addition\, recent advances in reference clock generation will also be disc
 ussed as it is crucial for high performance PLLs.\n\nCo-sponsored by: Soli
 d-State Circuits\n\nSpeaker(s): Wanghua Wu\, \n\nRoom: 516\, Bldg: ICT\, U
 nniversity of Calgary\, Calgary\, Alberta\, Canada\, T2N1N4
LOCATION:Room: 516\, Bldg: ICT\, Unniversity of Calgary\, Calgary\, Alberta
 \, Canada\, T2N1N4
ORGANIZER:lbelosto@ucalgary.ca
SEQUENCE:5
SUMMARY:Recent Trends and Advances in High Performance Fractional-N PLL Des
 ign
URL;VALUE=URI:https://events.vtools.ieee.org/m/325661
X-ALT-DESC:Description: &lt;br /&gt;&lt;p&gt;High performance fractional-N phase-locked
  loops (PLLs) are essential elements of any advanced electronic systems. I
 n recent years\, both analog and all-digital PLLs employing sampling or su
 b-sampling phase detector have gained popularity and demonstrated below 10
 0-fs integrated jitter and superior figure-of-merit. This talk focuses on 
 this PLL architecture and elaborates the advanced design techniques to ach
 ieve low jitter\, low fractional spurs\, fast locking\, and low power oper
 ation. Both circuits design and digital calibration techniques will be pre
 sented in detail. In addition\, recent advances in reference clock generat
 ion will also be discussed as it is crucial for high performance PLLs.&lt;/p&gt;
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