BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/New_York BEGIN:DAYLIGHT DTSTART:20220313T030000 TZOFFSETFROM:-0500 TZOFFSETTO:-0400 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:EDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20221106T010000 TZOFFSETFROM:-0400 TZOFFSETTO:-0500 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:EST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20221102T224535Z UID:211D65CC-709F-476D-BC4B-8C4251FB5CA4 DTSTART;TZID=America/New_York:20221027T183000 DTEND;TZID=America/New_York:20221027T203000 DESCRIPTION:On Thursday\, October 27\, 2022\, the [IEEE Consultants’ Netw ork of Northern New Jersey](https://www.technologyontap.org/) will host a presentation on Open Source Chip Design with Dr Mehdi Saligane on Zoom.\n\ nAbout the Topic\n\nLowering the barriers to chip design using OpenFASOC: Fully Autonomous System-on-Chip (FASoC) tool is a DARPA-funded project wit hin the IDEA program. Its main objective is to address the need for analog compilers. The framework relies on the place and route digital flow which has long been extensively automated while most analog flows are still ext remely reliant on manual design. This lack of analog automation tools lead s to long design cycles and costs. FASoC addresses this need and uses a ce ll-based analog design generation methodology to generate different analog and mixed-signal (AMS) blocks (i.e.\, PLL\, LDO\, DC-DC converters\, Temp erature Sensors\, etc.).\n\nA few SoCs have been taped out in the SkyWater 130 nm\, BI-CMOS 130 nm\, TSMC 65 nm and Globalfoundries 12 nm foundry pr ocess nodes. OpenFASOC has been built on top of OpenROAD for push-button l ayout generation as part of the current open source effort. This talk will go through a few of our open-source analog generators (Temperature Sensor \, Switched-Cap DC-DC Converter\, etc.)\, our implemented designs in Googl e’s free shuttles MPW-I / II and our GF12LP tapeout of the OpenTitan SoC which heavily used open source tooling.\n\nAbout the Speaker\n\n[Mehdi Sa ligane](https://www.linkedin.com/in/mehdi-saligane/) is a Research Scienti st in the Department of Electrical Engineering and Computer Science at the University of Michigan. He received his Masters\, and Ph.D. degrees in el ectrical and computer engineering from the University of Grenoble and Aix- Marseille in 2011 and 2016\, respectively. He worked at STMicroelectronics \, in France\, as a Research Engineer from 2010 to 2015\, and after comple ting his Ph.D.\, he joined the [Michigan Integrated Circuits Lab](https:// micl.engin.umich.edu/) at the University of Michigan. Dr. Saligane’s cur rent research interests are in low-power and energy-efficient IC design wi th a recent focus on open-source EDA and analog and mixed-signal IC design automation. He currently serves as chair of the Analog Working Group and\ , as a member of the Technical Steering Committee at [CHIPS Alliance](http s://chipsalliance.org/)\, and as a technical member of SSCS’ open source ecosystem.\n\nCNNNJ Invites You to Join the Network\n\nFounded in 1992\, the IEEE Consultants Network of Northern NJ (CNNNJ) encourages and promote s the use of independent technical consultants by business and industry. T he CNNNJ invites all engineers engaged in independent practice to join its ranks. For more details on member benefits and admission requirements\, p lease visit our website at technologyontap.org.\n\nAgenda: \nIntroductions \nSpeaker presentation\nDemo\nAudience questions welcomed\nNetworking\n\nV irtual: https://events.vtools.ieee.org/m/328096 LOCATION:Virtual: https://events.vtools.ieee.org/m/328096 ORGANIZER:info@technologyontap.org SEQUENCE:7 SUMMARY:Open Source chip design URL;VALUE=URI:https://events.vtools.ieee.org/m/328096 X-ALT-DESC:Description: <br /><p style="margin-top: 0px\; margin-bottom: 16 px\; color: #333333\; font-family: 'Helvetica Neue'\, Helvetica\, 'Segoe U I'\, Arial\, freesans\, sans-serif\; font-size: 16px\; font-style: normal\ ; font-variant-ligatures: normal\; font-variant-caps: normal\; font-weight : 400\; letter-spacing: normal\; orphans: 2\; text-align: start\; text-ind ent: 0px\; text-transform: none\; white-space: normal\; widows: 2\; word-s pacing: 0px\; -webkit-text-stroke-width: 0px\; background-color: #ffffff\; text-decoration-style: initial\; text-decoration-color: initial\;">On Thu rsday\, October 27\, 2022\, the&nbsp\;<a style="color: #0088cc\; text-deco ration: none\;" href="https://www.technologyontap.org/">IEEE Consultants&r squo\; Network of Northern New Jersey</a>&nbsp\;will host a presentation o n Open Source Chip Design with Dr Mehdi Saligane on Zoom.</p>\n<h3 id="abo ut-the-topic" class="mume-header" style="line-height: 1.2\; margin-top: 1e m\; margin-bottom: 16px\; color: #000000\; font-size: 1.5em\; font-weight: 600\; font-family: 'Helvetica Neue'\, Helvetica\, 'Segoe UI'\, Arial\, fr eesans\, sans-serif\; font-style: normal\; font-variant-ligatures: normal\ ; font-variant-caps: normal\; letter-spacing: normal\; orphans: 2\; text-a lign: start\; text-indent: 0px\; text-transform: none\; white-space: norma l\; widows: 2\; word-spacing: 0px\; -webkit-text-stroke-width: 0px\; backg round-color: #ffffff\; text-decoration-style: initial\; text-decoration-co lor: initial\;">About the Topic</h3>\n<p style="margin-top: 0px\; margin-b ottom: 16px\; color: #333333\; font-family: 'Helvetica Neue'\, Helvetica\, 'Segoe UI'\, Arial\, freesans\, sans-serif\; font-size: 16px\; font-style : normal\; font-variant-ligatures: normal\; font-variant-caps: normal\; fo nt-weight: 400\; letter-spacing: normal\; orphans: 2\; text-align: start\; text-indent: 0px\; text-transform: none\; white-space: normal\; widows: 2 \; word-spacing: 0px\; -webkit-text-stroke-width: 0px\; background-color: #ffffff\; text-decoration-style: initial\; text-decoration-color: initial\ ;">Lowering the barriers to chip design using OpenFASOC: Fully Autonomous System-on-Chip (FASoC) tool is a DARPA-funded project within the IDEA prog ram. Its main objective is to address the need for analog compilers. The f ramework relies on the place and route digital flow which has long been ex tensively automated while most analog flows are still extremely reliant on manual design. This lack of analog automation tools leads to long design cycles and costs. FASoC addresses this need and uses a cell-based analog d esign generation methodology to generate different analog and mixed-signal (AMS) blocks (i.e.\, PLL\, LDO\, DC-DC converters\, Temperature Sensors\, etc.).</p>\n<p style="margin-top: 0px\; margin-bottom: 16px\; color: #333 333\; font-family: 'Helvetica Neue'\, Helvetica\, 'Segoe UI'\, Arial\, fre esans\, sans-serif\; font-size: 16px\; font-style: normal\; font-variant-l igatures: normal\; font-variant-caps: normal\; font-weight: 400\; letter-s pacing: normal\; orphans: 2\; text-align: start\; text-indent: 0px\; text- transform: none\; white-space: normal\; widows: 2\; word-spacing: 0px\; -w ebkit-text-stroke-width: 0px\; background-color: #ffffff\; text-decoration -style: initial\; text-decoration-color: initial\;">A few SoCs have been t aped out in the SkyWater 130 nm\, BI-CMOS 130 nm\, TSMC 65 nm and Globalfo undries 12 nm foundry process nodes. OpenFASOC has been built on top of Op enROAD for push-button layout generation as part of the current open sourc e effort. This talk will go through a few of our open-source analog genera tors (Temperature Sensor\, Switched-Cap DC-DC Converter\, etc.)\, our impl emented designs in Google&rsquo\;s free shuttles MPW-I / II and our GF12LP tapeout of the OpenTitan SoC which heavily used open source tooling.</p>\ n<h3 id="about-the-speaker" class="mume-header" style="line-height: 1.2\; margin-top: 1em\; margin-bottom: 16px\; color: #000000\; font-size: 1.5em\ ; font-weight: 600\; font-family: 'Helvetica Neue'\, Helvetica\, 'Segoe UI '\, Arial\, freesans\, sans-serif\; font-style: normal\; font-variant-liga tures: normal\; font-variant-caps: normal\; letter-spacing: normal\; orpha ns: 2\; text-align: start\; text-indent: 0px\; text-transform: none\; whit e-space: normal\; widows: 2\; word-spacing: 0px\; -webkit-text-stroke-widt h: 0px\; background-color: #ffffff\; text-decoration-style: initial\; text -decoration-color: initial\;">About the Speaker</h3>\n<p style="margin-top : 0px\; margin-bottom: 16px\; color: #333333\; font-family: 'Helvetica Neu e'\, Helvetica\, 'Segoe UI'\, Arial\, freesans\, sans-serif\; font-size: 1 6px\; font-style: normal\; font-variant-ligatures: normal\; font-variant-c aps: normal\; font-weight: 400\; letter-spacing: normal\; orphans: 2\; tex t-align: start\; text-indent: 0px\; text-transform: none\; white-space: no rmal\; widows: 2\; word-spacing: 0px\; -webkit-text-stroke-width: 0px\; ba ckground-color: #ffffff\; text-decoration-style: initial\; text-decoration -color: initial\;"><a style="color: #0088cc\; text-decoration: none\;" hre f="https://www.linkedin.com/in/mehdi-saligane/">Mehdi Saligane</a>&nbsp\;i s a Research Scientist in the Department of Electrical Engineering and Com puter Science at the University of Michigan. He received his Masters\, and Ph.D. degrees in electrical and computer engineering from the University of Grenoble and Aix-Marseille in 2011 and 2016\, respectively. He worked a t STMicroelectronics\, in France\, as a Research Engineer from 2010 to 201 5\, and after completing his Ph.D.\, he joined the&nbsp\;<a style="color: #0088cc\; text-decoration: none\;" href="https://micl.engin.umich.edu/">Mi chigan Integrated Circuits Lab</a>&nbsp\;at the University of Michigan. Dr . Saligane&rsquo\;s current research interests are in low-power and energy -efficient IC design with a recent focus on open-source EDA and analog and mixed-signal IC design automation. He currently serves as chair of the An alog Working Group and\, as a member of the Technical Steering Committee a t&nbsp\;<a style="color: #0088cc\; text-decoration: none\;" href="https:// chipsalliance.org/">CHIPS Alliance</a>\, and as a technical member of SSCS &rsquo\; open source ecosystem.</p>\n<h3 id="cnnnj-invites-you-to-join-the -network" class="mume-header" style="line-height: 1.2\; margin-top: 1em\; margin-bottom: 16px\; color: #000000\; font-size: 1.5em\; font-weight: 600 \; font-family: 'Helvetica Neue'\, Helvetica\, 'Segoe UI'\, Arial\, freesa ns\, sans-serif\; font-style: normal\; font-variant-ligatures: normal\; fo nt-variant-caps: normal\; letter-spacing: normal\; orphans: 2\; text-align : start\; text-indent: 0px\; text-transform: none\; white-space: normal\; widows: 2\; word-spacing: 0px\; -webkit-text-stroke-width: 0px\; backgroun d-color: #ffffff\; text-decoration-style: initial\; text-decoration-color: initial\;">CNNNJ Invites You to Join the Network</h3>\n<p style="margin-t op: 0px\; margin-bottom: 16px\; color: #333333\; font-family: 'Helvetica N eue'\, Helvetica\, 'Segoe UI'\, Arial\, freesans\, sans-serif\; font-size: 16px\; font-style: normal\; font-variant-ligatures: normal\; font-variant -caps: normal\; font-weight: 400\; letter-spacing: normal\; orphans: 2\; t ext-align: start\; text-indent: 0px\; text-transform: none\; white-space: normal\; widows: 2\; word-spacing: 0px\; -webkit-text-stroke-width: 0px\; background-color: #ffffff\; text-decoration-style: initial\; text-decorati on-color: initial\;">Founded in 1992\, the IEEE Consultants Network of Nor thern NJ (CNNNJ) encourages and promotes the use of independent technical consultants by business and industry. The CNNNJ invites all engineers enga ged in independent practice to join its ranks. For more details on member benefits and admission requirements\, please visit our website at&nbsp\;<a style="color: #0088cc\; text-decoration: none\;" href="http://technologyo ntap.org">technologyontap.org</a>.</p><br /><br />Agenda: <br /><p>Introdu ctions<br />Speaker presentation<br />Demo<br />Audience questions welcome d<br />Networking</p> END:VEVENT END:VCALENDAR