BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/New_York BEGIN:DAYLIGHT DTSTART:20220313T030000 TZOFFSETFROM:-0500 TZOFFSETTO:-0400 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:EDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20221106T010000 TZOFFSETFROM:-0400 TZOFFSETTO:-0500 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:EST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20230106T201011Z UID:E6C0AC6A-FACD-44D8-9A8C-87680EC8B5EA DTSTART;TZID=America/New_York:20221027T183000 DTEND;TZID=America/New_York:20221027T204500 DESCRIPTION:Lowering the barriers to chip design using OpenFASOC: Fully Aut onomous System-on-Chip (FASoC) tool is a DARPA-funded project within the I DEA program. Its main objective is to address the need for analog compiler s. The framework relies on the place and route digital flow which has long been extensively automated while most analog flows are still extremely re liant on manual design. This lack of analog automation tools leads to long design cycles and costs. FASoC addresses this need and uses a cell-based analog design generation methodology to generate different analog and mixe d-signal (AMS) blocks (i.e.\, PLL\, LDO\, DC-DC converters\, Temperature S ensors\, etc.).\n\nA few SoCs have been taped out in the SkyWater 130 nm\, BI-CMOS 130 nm\, TSMC 65 nm and Globalfoundries 12 nm foundry process nod es. OpenFASOC has been built on top of OpenROAD for push-button layout gen eration as part of the current open source effort. This talk will go throu gh a few of our open-source analog generators (Temperature Sensor\, Switch ed-Cap DC-DC Converter\, etc.)\, our implemented designs in Google's free shuttles MPW-I / II and our GF12LP tapeout of the OpenTitan SoC which heav ily used open source tooling.\n\nCo-sponsored by: IEEE Consultants’ Netw ork of Northern New Jersey\n\nSpeaker(s): Dr. Saligane\, \n\nAgenda: \n6:3 0 PM to 8:30 PM - Presentation\n\n8:30+ networking session on Zoom\n\nVirt ual: https://events.vtools.ieee.org/m/328368 LOCATION:Virtual: https://events.vtools.ieee.org/m/328368 ORGANIZER:info@technologyontap.org SEQUENCE:3 SUMMARY:Open Source Chip Design URL;VALUE=URI:https://events.vtools.ieee.org/m/328368 X-ALT-DESC:Description: <br /><p>Lowering the barriers to chip design using OpenFASOC: Fully Autonomous System-on-Chip (FASoC) tool is a DARPA-funded project within the IDEA program. Its main objective is to address the nee d for analog compilers. The framework relies on the place and route digita l flow which has long been extensively automated while most analog flows a re still extremely reliant on manual design. This lack of analog automatio n tools leads to long design cycles and costs. FASoC addresses this need a nd uses a cell-based analog design generation methodology to generate diff erent analog and mixed-signal (AMS) blocks (i.e.\, PLL\, LDO\, DC-DC conve rters\, Temperature Sensors\, etc.).</p>\n<p>A few SoCs have been taped ou t in the SkyWater 130 nm\, BI-CMOS 130 nm\, TSMC 65 nm and Globalfoundries 12 nm foundry process nodes. OpenFASOC has been built on top of OpenROAD for push-button layout generation as part of the current open source effor t. This talk will go through a few of our open-source analog generators (T emperature Sensor\, Switched-Cap DC-DC Converter\, etc.)\, our implemented designs in Google's free shuttles MPW-I / II and our GF12LP tapeout of th e OpenTitan SoC which heavily used open source tooling.</p><br /><br />Age nda: <br /><p><span style="color: #333333\;"><span style="font-size: 16px\ ;">6:30 PM to 8:30 PM - Presentation</span></span></p>\n<p><span style="co lor: #333333\;"><span style="font-size: 16px\;">8:30+ networking session o n Zoom</span></span></p> END:VEVENT END:VCALENDAR