BEGIN:VCALENDAR
VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
BEGIN:DAYLIGHT
DTSTART:20230312T030000
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3
TZNAME:PDT
END:DAYLIGHT
BEGIN:STANDARD
DTSTART:20221106T010000
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11
TZNAME:PST
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20221119T045731Z
UID:AD3FEDDE-CD4E-4514-A822-E1DBD1A5CFB9
DTSTART;TZID=America/Los_Angeles:20221118T120000
DTEND;TZID=America/Los_Angeles:20221118T130000
DESCRIPTION:This presentation will discuss the main challenges in the physi
 cal implementation\, design\, hierarchical modelling and simulation of the
  scalable qubit array and of the cryogenic control and readout electronics
  for future Quantum Processors with millions of qubits manufactured in com
 mercial FDSOI and FinFET foundry technologies. Impact of process manufactu
 ring rules restrictions and process variation on qubit design and modellin
 g\, circuit heat dissipation and layout miniaturization to fit the qubit a
 rray pitch\, qubit-to-qubit crosstalk\, and the need for atomistic\, class
 ical\, and behavioural qubit simulation and modelling will be covered in d
 etail.\n\nCo-sponsored by: Circuits and Systems Society - CASS-SCV\n\nSpea
 ker(s): Dr. Sorin P. Voinigescu\, \n\nAgenda: \nThis presentation will dis
 cuss the main challenges in the physical implementation\, design\, hierarc
 hical modelling and simulation of the scalable qubit array and of the cryo
 genic control and readout electronics for future Quantum Processors with m
 illions of qubits manufactured in commercial FDSOI and FinFET foundry tech
 nologies. Impact of process manufacturing rules restrictions and process v
 ariation on qubit design and modelling\, circuit heat dissipation and layo
 ut miniaturization to fit the qubit array pitch\, qubit-to-qubit crosstalk
 \, and the need for atomistic\, classical\, and behavioural qubit simulati
 on and modelling will be covered in detail.\n\nVirtual: https://events.vto
 ols.ieee.org/m/328892
LOCATION:Virtual: https://events.vtools.ieee.org/m/328892
ORGANIZER:hiuyung.wong@sjsu.edu
SEQUENCE:2
SUMMARY:IEEE-EDS Seminar - Design and Modelling Challenges for Very Large-S
 cale Integrated Quantum Processors in Foundry CMOS Technologies by Sorin P
 . Voinigescu
URL;VALUE=URI:https://events.vtools.ieee.org/m/328892
X-ALT-DESC:Description: <br /><p>This presentation will discuss the main ch
 allenges in the physical implementation\, design\, hierarchical modelling 
 and simulation of the scalable qubit array and of the cryogenic control an
 d readout electronics for future Quantum Processors with millions of qubit
 s manufactured in commercial FDSOI and FinFET foundry technologies. Impact
  of process manufacturing rules restrictions and process variation on qubi
 t design and modelling\, circuit heat dissipation and layout miniaturizati
 on to fit the qubit array pitch\, qubit-to-qubit crosstalk\, and the need 
 for atomistic\, classical\, and behavioural qubit simulation and modelling
  will be covered in detail.</p><br /><br />Agenda: <br /><p>This presentat
 ion will discuss the main challenges in the physical implementation\, desi
 gn\, hierarchical modelling and simulation of the scalable qubit array and
  of the cryogenic control and readout electronics for future Quantum Proce
 ssors with millions of qubits manufactured in commercial FDSOI and FinFET 
 foundry technologies. Impact of process manufacturing rules restrictions a
 nd process variation on qubit design and modelling\, circuit heat dissipat
 ion and layout miniaturization to fit the qubit array pitch\, qubit-to-qub
 it crosstalk\, and the need for atomistic\, classical\, and behavioural qu
 bit simulation and modelling will be covered in detail.</p>
END:VEVENT
END:VCALENDAR