BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Europe/Warsaw BEGIN:DAYLIGHT DTSTART:20220327T030000 TZOFFSETFROM:+0100 TZOFFSETTO:+0200 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=3 TZNAME:CEST END:DAYLIGHT BEGIN:STANDARD DTSTART:20221030T020000 TZOFFSETFROM:+0200 TZOFFSETTO:+0100 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=10 TZNAME:CET END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20221102T102558Z UID:825598C3-A617-4D18-B176-56B6906DC176 DTSTART;TZID=Europe/Warsaw:20221027T153000 DTEND;TZID=Europe/Warsaw:20221028T190000 DESCRIPTION:Prof. Bogdan Staszewski opowie o projektowaniu układów All-Di gital PLL w nowoczesnych technologiach mikroelektronicznych.\n\nAbstract: The past two decades has seen proliferation of all-digital phase-locked lo ops (ADPLL) for RF and highperformance frequency synthesis due to their cl ear benefits of flexibility\, reconfigurability\, transfer function precis ion\, settling speed\, frequency modulation capability\, and amenability t o integration withdigital baseband and application processors. When implem ented in nanoscale CMOS\, the ADPLL also exhibits advantages of better per formance\, lower power consumption\, lower area and cost over the traditio nal analog-intensive charge-pump PLL. In a typical ADPLL\, a traditional V CO got directly replaced by a digitally controlled oscillator (DCO) for ge nerating an output variable clock\, a traditional phase/frequency detector and a charge pump got replaced by a time-to-digital converter (TDC) for d etecting phase departures of the variable clock versus the frequency refer ence (FREF) clock\, and an analog loop RC filter got replaced with a digit al loop filter. The conversion gains of the DCO and TDC circuits are readi ly estimated and compensated using “free” but powerful digital logic.\ n\nRobert Bogdan Staszewski received the BSc (summa cum laude)\, MSc and P hD degrees from the University of Texas at Dallas in 1991\, 1992 and 2002\ , respectively. From 1991 to 1995 he was with Alcatel Network Systems in R ichardson\, TX\, USA\, working on SONET cross-connect systems for fiber op tics communications. He joined Texas Instruments in Dallas\, TX\, USA\, in 1995 where he was elected Distinguished Member of Technical Staff (2% of the technical population). Between 1995 and 1999\, he was engaged in advan ced CMOS read channel development for hard disk drives. In 1999 he co-star ted a Digital RF Processor (DRP) group within Texas Instruments with a mis sion to invent new digitally intensive approaches to traditional RF functi ons for integrated radios in deep-submicron CMOS. He served as a CTO of th e DRP group between 2007 and 2009. In 2009\, he joined Delft University of Technology in the Netherlands where he is currently a guest Full Professo r. Since 2014\, he has been a Full Professor with University College Dubli n in Ireland. He has authored and co-authored seven books\, 11 book chapte rs\, 160 journal and 220 conference publications\, and holds 220 issued US patents. His research interests include nanoscale CMOS architectures and circuits for frequency synthesizers\, transmitters and receivers\, as well as quantum computers. He is an IEEE Fellow and recipient of IEEE Circuits and Systems Industrial Pioneer Award.\n\nCo-sponsored by: Silicon Creatio ns\n\nBldg: D-16\, ACMIN\, Kawiory 30\, Kraków\, Malopolskie\, Poland LOCATION:Bldg: D-16\, ACMIN\, Kawiory 30\, Kraków\, Malopolskie\, Poland ORGANIZER:krzysztof.kasinski@siliconcr.com SEQUENCE:2 SUMMARY:Kurs na temat projektowania All-Digital PLL URL;VALUE=URI:https://events.vtools.ieee.org/m/329452 X-ALT-DESC:Description: <br /><div class="x_elementToProof">Prof. Bogdan St aszewski opowie o projektowaniu układ&oacute\;w All-Digital PLL w nowocze snych technologiach mikroelektronicznych.</div>\n<div class="x_elementToPr oof">&nbsp\;</div>\n<div class="x_elementToProof x_ContentPasted0"><strong class="x_ContentPasted0">Abstract:&nbsp\;</strong>The past two decades ha s seen proliferation of all-digital phase-locked loops (ADPLL) for RF and highperformance frequency synthesis due to their clear benefits of flexibi lity\, reconfigurability\, transfer function precision\, settling speed\, frequency modulation capability\, and amenability to integration withdigit al baseband and application processors. When implemented in nanoscale CMOS \, the ADPLL also exhibits advantages of better performance\, lower power consumption\, lower area and cost over the traditional analog-intensive ch arge-pump PLL. In a typical ADPLL\, a traditional VCO got directly replace d by a digitally controlled oscillator (DCO) for generating an output vari able clock\, a traditional phase/frequency detector and a charge pump got replaced by a time-to-digital converter (TDC) for detecting phase departur es of the variable clock versus the frequency reference (FREF) clock\, and an analog loop RC filter got replaced with a digital loop filter. The con version gains of the DCO and TDC circuits are readily estimated and compen sated using &ldquo\;free&rdquo\; but powerful digital logic.</div>\n<div c lass="x_elementToProof x_ContentPasted0">&nbsp\;</div>\n<div class="x_elem entToProof x_ContentPasted0"><span class="x_ui-text x_eh x_ei x_lr x_ls x_ lx x_ContentPasted1" dir="auto">Robert Bogdan Staszewski received the BSc (summa cum laude)\, MSc and PhD degrees from the University of Texas at Da llas in 1991\, 1992 and 2002\, respectively. From 1991 to 1995 he was with Alcatel Network Systems in Richardson\, TX\, USA\, working on SONET cross -connect systems for fiber optics communications. He joined Texas Instrume nts in Dallas\, TX\, USA\, in 1995 where he was elected Distinguished Memb er of Technical Staff (2% of the technical population). Between 1995 and 1 999\, he was engaged in advanced CMOS read channel development for hard di sk drives. In 1999 he co-started a Digital RF Processor (DRP) group within Texas Instruments with a mission to invent new digitally intensive approa ches to traditional RF functions for integrated radios in deep-submicron C MOS. He served as a CTO of the DRP group between 2007 and 2009. In 2009\, he joined Delft University of Technology in the Netherlands where he is cu rrently a guest Full Professor. Since 2014\, he has been a Full Professor with University College Dublin in Ireland. He has authored and co-authored seven books\, 11 book chapters\, 160 journal and 220 conference publicati ons\, and holds 220 issued US patents. His research interests include nano scale CMOS architectures and circuits for frequency synthesizers\, transmi tters and receivers\, as well as quantum computers. He is an IEEE Fellow a nd recipient of IEEE Circuits and Systems Industrial Pioneer Award.</span> </div> END:VEVENT END:VCALENDAR