BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/New_York BEGIN:DAYLIGHT DTSTART:20230312T030000 TZOFFSETFROM:-0500 TZOFFSETTO:-0400 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:EDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20221106T010000 TZOFFSETFROM:-0400 TZOFFSETTO:-0500 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:EST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20230109T230407Z UID:E93D2218-20E6-4435-98AD-67B1CD65A0B5 DTSTART;TZID=America/New_York:20221121T180000 DTEND;TZID=America/New_York:20221121T193000 DESCRIPTION:Power has become the key driving force in processor as well AI specific accelerator designs as the frequency scale-up is reaching saturat ion. In order to achieve low power system\, circuit and technology co-desi gn is essential. This talk focuses on related technology and important cir cuit techniques for nanoscale VLSI circuits. Achieving low power and high performance simultaneously is always difficult. Technology has seen major shifts from bulk to SOI and then to non-planar devices such as FinFET and Trigates.\n\nThis talk consists of pros and cons analysis on technology fr om power perspective and various techniques to exploit lower power. As the technology pushes towards sub-7nm era\, process variability and geometric variation in devices can cause variation in power. The reliability also p lays an important role in the power-performance envelope. This talk also r eviews the methodology to capture such effects and describes all the power components. All the key areas of low power optimization such as reduction in active power\, leakage power\, short circuit power and collision power are covered. Usage of clock gating\, power gating\, longer channel\, mult i-Vt design\, stacking\, header-footer device techniques and other methods are described for logic and memory used for processors and AI. Finally th e talk summarizes key challenges in achieving low power.\n\nIn addition th e tutorial gives a brief overview of predictive failure analytics used in nm Technology. Process and environmental variations impact circuit behavio r it is important to model their effects to build robust circuits. The tut orial describe how key statistical techniques can be effectively used to a nalyze and build robust circuits.\n\nSpeaker(s): Dr. Rajiv Joshi\, \n\nAge nda: \nThe event will start at 18:00PM EST and the talk will start at 18:1 0PM EST.\n\nRoom: BA2155\, Bldg: Bahen Centre for Information Technology\, 40 St George St \, Toronto\, Ontario\, Canada\, M5S 2E4\, Virtual: https: //events.vtools.ieee.org/m/331087 LOCATION:Room: BA2155\, Bldg: Bahen Centre for Information Technology\, 40 St George St \, Toronto\, Ontario\, Canada\, M5S 2E4\, Virtual: https://ev ents.vtools.ieee.org/m/331087 ORGANIZER:durand.jarrettamor@ieee.org SEQUENCE:18 SUMMARY:IEEE EDS Distinguished Lecture: Low Power Design and Predictive Fai lure Analytics in Silicon in nm Era URL;VALUE=URI:https://events.vtools.ieee.org/m/331087 X-ALT-DESC:Description: <br /><p>Power has become the key driving force in processor as well AI specific accelerator designs as the frequency scale-u p is reaching saturation. In order to achieve low power system\, circuit a nd technology co-design is essential. This talk focuses on related technol ogy and important circuit techniques for nanoscale VLSI circuits. Achievin g low power and high performance simultaneously is always difficult. Techn ology has seen major shifts from bulk to SOI and then to non-planar device s such as FinFET and Trigates.</p>\n<p>This talk consists of pros and cons analysis on technology from power perspective and various techniques to e xploit lower power. As the technology pushes towards sub-7nm era\, process variability and geometric variation in devices can cause variation in pow er. The reliability also plays an important role in the power-performance envelope. This talk also reviews the methodology to capture such effects a nd describes all the power components. All the key areas of low power opti mization such as reduction in active power\, leakage power\, short circuit power and collision power are covered. Usage of clock gating\, power gati ng\, longer channel\, multi-Vt design\, stacking\, header-footer device te chniques and other methods are described for logic and memory used for pro cessors and AI. Finally the talk summarizes key challenges in achieving lo w power.</p>\n<p>In addition the tutorial gives a brief overview of predic tive failure analytics used in nm Technology. Process and environmental va riations impact circuit behavior it is important to model their effects to build robust circuits. The tutorial describe how key statistical techniqu es can be effectively used to analyze and build robust circuits.</p><br /> <br />Agenda: <br /><p>The event will start at 18:00PM EST and the talk wi ll start at 18:10PM EST.</p> END:VEVENT END:VCALENDAR