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PRODID:IEEE vTools.Events//EN
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TZID:America/Mexico_City
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DTSTART:20221030T010000
TZOFFSETFROM:-0500
TZOFFSETTO:-0600
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BEGIN:VEVENT
DTSTAMP:20240105T045555Z
UID:F897767D-3B12-4D82-B9EB-3A70191E7004
DTSTART;TZID=America/Mexico_City:20221208T160000
DTEND;TZID=America/Mexico_City:20221208T170000
DESCRIPTION:We are in the age of ubiquitous compute – from hand-held devi
 ces to the cloud. This drives demand for high-speed data transfer between 
 and within the microchips that are in the systems that define this distrib
 uted compute infrastructure. Input/Output IPs that enable this data transf
 er are implemented using a mixture of both digital and analog circuitry. O
 ver the past few decades\, we have seen continued acceleration in bandwidt
 h requirements for Input/Output (IO) IP that support these high data trans
 fer rates. At the same time Silicon Technology nodes continue to scale to 
 provide the performance required for compute. This scaling is particularly
  challenging for analog circuitry which is sensitive to process variation.
  The combination of technology scaling and increasing bandwidth requiremen
 ts has driven acceleration of complexity in IO Design and dependence on fi
 rmware for training and calibration. In this presentation the author will 
 review Technology Scaling and its impact on analog circuit design and impl
 ementation. He will talk about the challenges he has observed in ensuring 
 the delivery of high-quality IO IPs in these advanced nodes. Finally\, he 
 will propose some solutions and future directions he believes necessary to
  overcome these challenges.\n\nCo-sponsored by: Intel Guadalajara\n\nSpeak
 er(s): Intel Princ. Eng. Daudi Onsongo\, \n\nVirtual: https://events.vtool
 s.ieee.org/m/335072
LOCATION:Virtual: https://events.vtools.ieee.org/m/335072
ORGANIZER:josechavez@iteso.mx
SEQUENCE:3
SUMMARY:Dr. Daudi Onsongo\, Achieving High Quality IO IP in Advanced Proces
 s Nodes
URL;VALUE=URI:https://events.vtools.ieee.org/m/335072
X-ALT-DESC:Description: <br /><p>We are in the age of ubiquitous compute &n
 dash\; from hand-held devices to the cloud.&nbsp\; This drives demand for 
 high-speed data transfer between and within the microchips that are in the
  systems that define this distributed compute infrastructure.&nbsp\; Input
 /Output IPs that enable this data transfer are implemented using a mixture
  of both digital and analog circuitry.&nbsp\; Over the past few decades\, 
 we have seen continued acceleration in bandwidth requirements for Input/Ou
 tput (IO) IP that support these high data transfer rates.&nbsp\; At the sa
 me time Silicon Technology nodes continue to scale to provide the performa
 nce required for compute.&nbsp\; This scaling is particularly challenging 
 for analog circuitry which is sensitive to process variation.&nbsp\; The c
 ombination of technology scaling and increasing bandwidth requirements has
  driven acceleration of complexity in IO Design and dependence on firmware
  for training and calibration.&nbsp\; In this presentation the author will
  review Technology Scaling and its impact on analog circuit design and imp
 lementation.&nbsp\; He will talk about the challenges he has observed in e
 nsuring the delivery of high-quality IO IPs in these advanced nodes.&nbsp\
 ; Finally\, he will propose some solutions and future directions he believ
 es necessary to overcome these challenges.</p>
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