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DESCRIPTION:A Novel Simulation Flow for DDR5 Systems with Clocked Receivers
 \n\nThe behavioral simulation needs for DDR5 memory systems have changed s
 ignificantly since DDR4. The needs for modeling DFE equalization effects w
 ith significant clock uncertainty to capture key Signal Integrity effects 
 have added additional complexity to simulation flows. This presentation wi
 ll address these issues\, and the recent enhancements to IBIS and IBIS-AMI
 \, in the context of JEDEC specifications\, to make possible accurate and 
 successful DDR5 memory system design.\n\nMatthew Leslie (Siemens EDA)\nJus
 tin Butterfield (Micron Technology)\nRandy Wolff (Micron Technology)\n\nHy
 brid IBIS Summit\nSanta Clara\, CA\nFebruary 3\, 2023\n\nCo-sponsored by: 
 IBIS Open Forum\n\nAgenda: \n Motivations\n\n DDR5 Specification and
  SI\n\n DDR5 DRAM Device Models\n\n Clocked IBIS-AMI Time-Domain Sim
 ulation\n\n Advanced IBIS-AMI Flow\n\n Key Takeaways\n\nSanta Clara\
 , California\, United States\, Virtual: https://events.vtools.ieee.org/m/3
 47014
LOCATION:Santa Clara\, California\, United States\, Virtual: https://events
 .vtools.ieee.org/m/347014
ORGANIZER:wedge@ieee.org
SEQUENCE:8
SUMMARY:A Novel Simulation Flow for DDR5 Systems with Clocked Receivers
URL;VALUE=URI:https://events.vtools.ieee.org/m/347014
X-ALT-DESC:Description: &lt;br /&gt;&lt;p&gt;&lt;span style=&quot;font-size: 14pt\;&quot;&gt;&lt;strong&gt;A 
 Novel Simulation Flow for DDR5 Systems with Clocked Receivers&lt;/strong&gt;&lt;/sp
 an&gt;&lt;/p&gt;\n&lt;p&gt;The behavioral simulation needs for DDR5 memory systems have c
 hanged significantly since DDR4. The needs for modeling DFE equalization e
 ffects with significant clock uncertainty to capture key Signal Integrity 
 effects have added additional complexity to simulation flows. This present
 ation will address these issues\, and the recent enhancements to IBIS and 
 IBIS-AMI\, in the context of JEDEC specifications\, to make possible accur
 ate and successful DDR5 memory system design.&amp;nbsp\;&lt;/p&gt;\n&lt;p&gt;Matthew Lesli
 e (Siemens EDA)&lt;br /&gt;Justin Butterfield (Micron Technology)&lt;br /&gt;Randy Wol
 ff (Micron Technology)&amp;nbsp\;&lt;/p&gt;\n&lt;p&gt;Hybrid IBIS Summit&lt;br /&gt;Santa Clara\
 , CA&lt;br /&gt;February 3\, 2023&lt;br /&gt;&lt;br /&gt;&lt;/p&gt;&lt;br /&gt;&lt;br /&gt;Agenda: &lt;br /&gt;&lt;p&gt;
  Motivations&lt;/p&gt;\n&lt;p&gt; DDR5 Specification and SI&lt;/p&gt;\n&lt;p&gt; DDR5 DRA
 M Device Models&lt;/p&gt;\n&lt;p&gt; Clocked IBIS-AMI Time-Domain Simulation&lt;/p&gt;\n&lt;
 p&gt; Advanced IBIS-AMI Flow&lt;/p&gt;\n&lt;p&gt; Key Takeaways&lt;/p&gt;
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