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UID:B523F8FF-207E-412E-8C4B-876EF7191B90
DTSTART;TZID=Europe/Zurich:20230420T153000
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DESCRIPTION:Chiplet is a chip design method and heterogeneous integration i
 s a chip packaging method. Chiplet design and heterogeneous integration pa
 ckaging have been generated lots of tractions lately. For the next few yea
 rs\, we will see more implementations of a higher level of chiplet designs
  and heterogeneous integration packaging\, whether it is for cost\, time-t
 o-market\, performance\, form factor\, or power consumption. In this lectu
 re\, the following topics will be covered.\n\n- System-on-Chip (SoC)\n- Wh
 y Chiplet Design?\n- Chiplet Design and Heterogeneous Integration Packagin
 g\n\n- Chip partition and Heterogeneous Integration\n- Chip split and Hete
 rogeneous Integration\n- Advantages and Disadvantages\n- Lateral Communica
 tion between Chiplets (e.g.\, Bridges)\n\n- Bridge Embedded in Build-up Pa
 ckage Substrate\n- Bridge Embedded in Fan-Out EMC with RDLs\n- UCIe\n- Hyb
 rid Bonding Bridge\n- Chiplet Design and Heterogeneous Integration Packagi
 ng - Multiple System and Heterogeneous Integration\n\n- Multiple System an
 d Heterogeneous Integration with Package Substrate (2D IC Integration)\n- 
 Multiple System and Heterogeneous Integration with Thin Film layer on the 
 Package Substrate (2.1D IC Integration)\n- Multiple System and Heterogeneo
 us Integration with TSV-less (Organic) Interposer (2.3D IC Integration)\n-
  Multiple System and Heterogeneous Integration with Passive TSV-Interposer
  (2.5D IC Integration)\n- Multiple System and Heterogeneous Integration wi
 th Active TSV-Interposer (3D IC Integration)\n- Summary\n- Potential R&D T
 opics in Chiplet Design and Heterogeneous Integration Packaging\n\nCo-spon
 sored by: ETH Zurich\n\nSpeaker(s): John H Lau\, \n\nAgenda: \n15:30 -15:4
 5 - Welcome and Introduction\, - Chairman IEEE EPS and SSCS chapters Switz
 erland\n\n15:45 -17:00 - Lecture on "Chiplet Design and Heterogenous Integ
 ration Packaging" by Dr. John H Lau Unimicron Technology Corporation\n\n17
 :00 -18:00- Apero\n\nRoom: E-81 \, ETH Zurich\, Gloriastrasse 35\, Zurich\
 , Switzerland\, Switzerland
LOCATION:Room: E-81 \, ETH Zurich\, Gloriastrasse 35\, Zurich\, Switzerland
 \, Switzerland
ORGANIZER:rony.josejames@csem.ch
SEQUENCE:9
SUMMARY:Swiss IEEE EPS and SSCS Lecture- Chiplet Design and Heterogeneous I
 ntegration Packaging
URL;VALUE=URI:https://events.vtools.ieee.org/m/349080
X-ALT-DESC:Description: <br /><p>Chiplet is a chip design method and hetero
 geneous integration is a chip packaging method. Chiplet design and heterog
 eneous integration packaging have been generated lots of tractions lately.
  For the next few years\, we will see more implementations of a higher lev
 el of chiplet designs and heterogeneous integration packaging\, whether it
  is for cost\, time-to-market\, performance\, form factor\, or power consu
 mption. In this lecture\, the following topics will be covered.</p>\n<p>&n
 bsp\;</p>\n<ul>\n<li>System-on-Chip (SoC)</li>\n<li>Why Chiplet Design?</l
 i>\n<li>Chiplet Design and Heterogeneous Integration Packaging</li>\n<ul>\
 n<li>Chip partition and Heterogeneous Integration</li>\n<li>Chip split and
  Heterogeneous Integration</li>\n<li>Advantages and Disadvantages</li>\n</
 ul>\n<li>Lateral Communication between Chiplets (e.g.\, Bridges)</li>\n<ul
 >\n<li>Bridge Embedded in Build-up Package Substrate</li>\n<li>Bridge Embe
 dded in Fan-Out EMC with RDLs</li>\n<li>UCIe</li>\n<li>Hybrid Bonding Brid
 ge</li>\n</ul>\n<li>Chiplet Design and Heterogeneous Integration Packaging
  - Multiple System and Heterogeneous Integration</li>\n<ul>\n<li>Multiple 
 System and Heterogeneous Integration with Package Substrate (2D IC Integra
 tion)</li>\n<li>Multiple System and Heterogeneous Integration with Thin Fi
 lm layer on the Package Substrate (2.1D IC Integration)</li>\n<li>Multiple
  System and Heterogeneous Integration with TSV-less (Organic) Interposer (
 2.3D IC Integration)</li>\n<li>Multiple System and Heterogeneous Integrati
 on with Passive TSV-Interposer (2.5D IC Integration)</li>\n<li>Multiple Sy
 stem and Heterogeneous Integration with Active TSV-Interposer (3D IC Integ
 ration)</li>\n</ul>\n<li>Summary</li>\n<li>Potential R&amp\;D Topics in Ch
 iplet Design and Heterogeneous Integration Packaging</li>\n</ul><br /><br 
 />Agenda: <br /><p>15:30 -15:45 - Welcome and Introduction\, - Chairman IE
 EE EPS and SSCS chapters Switzerland&nbsp\;</p>\n<p>15:45 -17:00 - Lecture
  on "Chiplet Design and Heterogenous Integration Packaging" by Dr. John H 
 Lau Unimicron Technology Corporation</p>\n<p>17:00 -18:00- Apero</p>
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