BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/New_York BEGIN:DAYLIGHT DTSTART:20230312T030000 TZOFFSETFROM:-0500 TZOFFSETTO:-0400 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:EDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20231105T010000 TZOFFSETFROM:-0400 TZOFFSETTO:-0500 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:EST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20230323T093841Z UID:5AC72661-F905-4E45-A76E-EF96A0421D7F DTSTART;TZID=America/New_York:20230322T164500 DTEND;TZID=America/New_York:20230322T180000 DESCRIPTION:The crescent demand for performance and speed of the integrated circuits has led the semiconductor industry to focus on the ever-increasi ng number of integrated devices in the same chip. Since the middle of the 60s’\, this number has followed the Moore´s Law\, which states that the number of integrated devices should double every two years. With the proc ess of continuous dimensions reduction of the devices\, degraded behavior arose due to a harmful effect called short channel effects\, and also\, si licon has reached its limits with respect to the devices’ shrinkage. To keep the continuous development\, not only Moore´s law is observed to mai ntain the increase in devices’ integration in recent technologies\, but also new interconnect and packaging schemes and new compact layout rules t echniques have also become an interest in the research to maintain the dev elopment to supply the system´s demand.\n\nDuring the lecture\, the chara cteristics of the coupling effects that can arise with the reduction of th e distance between the devices will be outlined\, aiming at an optimizatio n of the space in the silicon wafer with a compact layout scheme.\n\nCo-sp onsored by: IEEE North Jersey Section\n\nSpeaker(s): Fernando Jose da Cost a \, \n\nAgenda: \nEvent Time: 4:45PM to 6:00 PM\n\nVenue: Kiernan Confere nce Room (ECE 202)\, ECEC\, NJIT\, Newark\n\nRefreshments: 4:45 PM\n\nTalk at 5:00 PM\n\nSeminar in ECE 202 All Welcome: There is no fee/charge for attending IEEE technical seminar. You don't have to be an IEEE Member to a ttend. Refreshment is free for all attendees. Please invite your friends a nd colleagues to take advantage of this Invited Distinguished Lecture.\n\n Room: 202\, Bldg: ECEC\, 154 Summit Street\, Newark\, NJ 07102\, NJIT\, Ne wark\, New Jersey\, United States\, 07102 LOCATION:Room: 202\, Bldg: ECEC\, 154 Summit Street\, Newark\, NJ 07102\, N JIT\, Newark\, New Jersey\, United States\, 07102 ORGANIZER:akpoddar@ieee.org SEQUENCE:2 SUMMARY:A Simulation Perspective: Cross-Coupling Effects analysis of device s for advanced technological nodes URL;VALUE=URI:https://events.vtools.ieee.org/m/350820 X-ALT-DESC:Description: <br /><p>The crescent demand for performance and sp eed of the integrated circuits has led the semiconductor industry to focus on the ever-increasing number of integrated devices in the same chip. Sin ce the middle of the 60s&rsquo\;\, this number has followed the Moore&acut e\;s Law\, which states that the number of integrated devices should doubl e every two years. With the process of continuous dimensions reduction of the devices\, degraded behavior arose due to a harmful effect called short channel effects\, and also\, silicon has reached its limits with respect to the devices&rsquo\; shrinkage.<strong><em> </em></strong>To keep the co ntinuous development\, not only Moore&acute\;s law is observed to maintain the increase in devices&rsquo\; integration in recent technologies\, but also new interconnect and packaging schemes and new compact layout rules t echniques have also become an interest in the research to maintain the dev elopment to supply the system&acute\;s demand.</p>\n<p>During the lecture\ , the characteristics of the coupling effects that can arise with the redu ction of the distance between the devices will be outlined\, aiming at an optimization of the space in the silicon wafer with a compact layout schem e.</p><br /><br />Agenda: <br /><p>Event Time: 4:45PM to 6:00 PM</p>\n<p>V enue: Kiernan Conference Room (ECE 202)\, &nbsp\;ECEC\, NJIT\, Newark</p>\ n<p>Refreshments: 4:45 PM</p>\n<p>Talk at 5:00 PM</p>\n<p>Seminar in ECE 2 02 All Welcome: There is no fee/charge for attending IEEE technical semina r. You don't have to be an IEEE Member to attend. Refreshment is free for all attendees. Please invite your friends and colleagues to take advantage of this Invited Distinguished Lecture.</p> END:VEVENT END:VCALENDAR