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DTSTAMP:20230430T201228Z
UID:71499033-B61E-4B2A-93A9-8DF3930D5A2E
DTSTART;TZID=America/New_York:20230331T120000
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DESCRIPTION:Abstract:\nWhile silicon scaling has reached astonishing levels
  over the last half century\, there has not been a corresponding level of 
 scaling in electronic packaging technology. However\, Artificial Intellige
 nce (AI) architectures are now changing the landscape\, increasingly movin
 g us towards advanced packaging technology\, especially Heterogeneous Inte
 gration (HI). What are these unique requirements of AI which are driving t
 he need for HI? What are some of the unique challenges in semiconductor an
 d packaging technologies that must be overcome to make this successful? Th
 is seminar will discuss key HI methods including interposers\, fan out waf
 er level processing\, silicon bridges\, and 3D integration. We will look a
 t their attributes as well as their challenges\, to determine how they can
  be leveraged to achieve AI architectures.\n\nSpeaker(s): Mukta Farooq\, \
 n\nAgenda: \n12:00 noon: pizza is served\n\n12:15PM: talk begins\n\n1PM: Q
 &A\, discussion\, refreshments\n\nRoom: GOL-2400\, Bldg: Golisano Hall (Co
 mputing)\, Rochester Institute of Technology\, Rochester\, New York\, Unit
 ed States\, 14623
LOCATION:Room: GOL-2400\, Bldg: Golisano Hall (Computing)\, Rochester Insti
 tute of Technology\, Rochester\, New York\, United States\, 14623
ORGANIZER:kdhemc@rit.edu
SEQUENCE:4
SUMMARY:Heterogeneous Integration to enable AI Architectures
URL;VALUE=URI:https://events.vtools.ieee.org/m/351803
X-ALT-DESC:Description: <br /><p><strong>Abstract:</strong><br />While sili
 con scaling has reached astonishing levels over the last half century\, th
 ere has not been a corresponding level of scaling in electronic packaging 
 technology. However\, Artificial Intelligence (AI) architectures are now c
 hanging the landscape\, increasingly moving us towards advanced packaging 
 technology\, especially Heterogeneous Integration (HI). What are these uni
 que requirements of AI which are driving the need for HI? What are some of
  the unique challenges in semiconductor and packaging technologies that mu
 st be overcome to make this successful? This seminar will discuss key HI m
 ethods including interposers\, fan out wafer level processing\, silicon br
 idges\, and 3D integration. We will look at their attributes as well as th
 eir challenges\, to determine how they can be leveraged to achieve AI arch
 itectures.</p><br /><br />Agenda: <br /><p>12:00 noon:&nbsp\; pizza is ser
 ved</p>\n<p>12:15PM:&nbsp\; talk begins</p>\n<p>1PM:&nbsp\; Q&amp\;A\, dis
 cussion\, refreshments</p>
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