BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Asia/Kolkata BEGIN:STANDARD DTSTART:19451014T230000 TZOFFSETFROM:+0630 TZOFFSETTO:+0530 TZNAME:IST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20230323T041043Z UID:A87A1904-8601-4E9A-AF56-F3F77AE03C74 DTSTART;TZID=Asia/Kolkata:20230123T093000 DTEND;TZID=Asia/Kolkata:20230128T163000 DESCRIPTION:A 5 day Faculty development programme on “VLSI Design using C adence EDA tools” was organized by Department of Electronics and Communi cation in association with IEEE student branch\, Department ECE\, Nitte Me enakshi Institute of Technology from 23rd to 28th January 2023.\n\nThe ina ugural event held on 23rd January was presided over by Dr. Ramachandra A C \, Professor & Head\, Department of Electronics & Communication Engineerin g\, Nitte Meenakshi Institute of Technology\, Bangalore\,\n\ngave a Brief talk on a journey from Knowledge to skill. It gave the participants ample number of tips to bridge the skill gaps between the academia and the indus try.\n\nThe Session started with Introduction to cadence tool by Dr.Sowmya Madhavan \, Dr.Naveen I G and Pradeep Kumar S which gave an insight on An alog and Mixed Signal IC Design Flow\, followed by an informative talk on CMOS Process Technology\, Design and analysis of Analog circuit and its im portance. Also gave hands on Basics of different tools available in VLSI\, invoking the tools Creating symbol and test bench for the inverter.\n\nOn Day 2\, Hands on Sessions By Entuple Technologies - Mr. Shivaprasad\, App lication Engineer\, Entuple Technologies was the resource person. The sess ion begins with designing Inverter at schematic level \, Inverter Test Cir cuit and different circuit level calculations like power dissipation \,Del ay and Area calculations were shown to participants to implement the IC de sign flows.\n\nThe afternoon session started by briefing about Schematic d esign and Mapping of schematic to Layout generation. Layout Level was veri fied with respect to Schematic in terms of Design Rule Check (DRC) \, Layo ut versus Schematic (LVS) and Parasitic Extraction.\n\nDay 3 of training o n Cadence started with discussion on doubts in layout. Demonstrated the Fr ont end design with 8 bit counter example. Initially\, the counter code wa s developed in Verilog and the test bench was written. Then NC launch tool was used to run the simulation. Post simulation\, synthesis was done to o btain the netlist.\n\nDuring the afternoon session\, all steps of Physical Design were demonstrated. Floorplanning\, Powerplanning\, Placement\, Clo ck Tree Synthesis\, Routing and Timing analysis were performed on the same RTL design. Finally\, generation of GDSII file also was shown.\n\nThe Day 4 continued with the Back annotation and had a brief interaction on Full Custom IC Design and Semi Custom IC Design. Given Insight of working with the FinFET Design. Also hands on was given on Design of analog circuit usi ng FinFET technology.\n\nThe Day 5 started with the how to implement the p rojects with the Cadence tool also different problem statements were discu ssed and finally concluded with discussion on Carrier Opportunities in VLS I Industry.\n\nFaculty development programme was attended by 12 participan ts.\n\nThe Event was successfully coordinated by the Dr.Sowmya Madhavan.\n \nDr. Parameshachari B. D.\n\nIEEE SB\, Professor\, ECE\, NMIT\n\nDr. Rama chandra A C\n\nProfessor and HOD\n\nDept. of ECE\, NMIT Bengaluru\n\nNitte Meenakshi Institute of Technology\, Bengaluru\, Karnataka\, India\, 56006 4 LOCATION:Nitte Meenakshi Institute of Technology\, Bengaluru\, Karnataka\, India\, 560064 ORGANIZER:paramesh@nmit.ac.in SEQUENCE:0 SUMMARY:VLSI Design using Cadence EDA tools URL;VALUE=URI:https://events.vtools.ieee.org/m/353770 X-ALT-DESC:Description: <br /><p>A 5 day Faculty development programme on < strong>&ldquo\;</strong><strong>VLSI Design using Cadence EDA tools</stron g><strong>&rdquo\; </strong>was organized by Department of Electronics and Communication in association with IEEE student branch\, Department ECE\, Nitte Meenakshi Institute of Technology from 23<sup>rd</sup> &nbsp\;to 28< sup>th</sup> January 2023.</p>\n<p>The inaugural event held on 23<sup>rd</ sup> &nbsp\;January was presided over by &nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp \;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&n bsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\ ;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nb sp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;<strong>Dr. Ramachandra A C</strong>\, Pro fessor &amp\; Head\, Department of Electronics &amp\; Communication Engine ering\,&nbsp\; Nitte Meenakshi Institute of Technology\, Bangalore\,</p>\n <p>gave a Brief talk on a journey from Knowledge to skill. It gave the par ticipants ample number of tips to bridge the skill gaps between the academ ia and the industry.</p>\n<p><strong>&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&n bsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\; </strong>The &nbsp\;Session started with <strong> Introduction to cadence tool </strong>by <strong>Dr.Sowmya Madhav an</strong> \,&nbsp\; <strong>Dr.Naveen I G and Pradeep Kumar S</strong> w hich gave an insight on Analog and Mixed Signal IC Design Flow\, followed by an informative talk on CMOS Process Technology\, Design and analysis of Analog circuit and its importance. Also gave hands on Basics of different tools available in VLSI\, invoking the tools Creating symbol and test ben ch for the inverter.</p>\n<p>&nbsp\;</p>\n<p>On Day 2\, <strong>Hands on S essions By Entuple Technologies - </strong>Mr. Shivaprasad\, Application E ngineer\, Entuple Technologies was the resource person. The session begins with designing Inverter at schematic level \, Inverter Test Circuit and d ifferent circuit level calculations like power dissipation \,Delay and Are a calculations were shown to participants to implement the IC design flows .</p>\n<p>The afternoon session started by briefing about Schematic design and Mapping of schematic to Layout generation. Layout Level was verified with respect to Schematic in terms of Design Rule Check (DRC) \, Layout ve rsus Schematic (LVS) and Parasitic Extraction.</p>\n<p><strong>Day 3</stro ng> of training on&nbsp\; Cadence started with discussion on doubts in lay out. Demonstrated the <strong>Front end design with 8 bit counter</strong> example.&nbsp\; Initially\, the counter code was developed in Verilog and the test bench was written. Then NC launch tool was used to run the simul ation. Post simulation\, synthesis was done to obtain the netlist.</p>\n<p >&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\;&nbsp\; During the afternoon se ssion\, all steps of Physical Design were demonstrated. Floorplanning\, Po werplanning\, Placement\, Clock Tree Synthesis\, Routing and Timing analys is were performed on the same RTL design. Finally\, generation of GDSII fi le also was shown.</p>\n<p><strong>The Day 4</strong> continued with the B ack annotation and had a brief interaction on Full Custom IC Design and Se mi Custom IC Design. Given Insight of working with the FinFET Design. Also hands on was given on Design of analog circuit using FinFET technology.</ p>\n<p><strong>The Day 5</strong> started with the how to implement the pr ojects with the Cadence tool also different problem statements were&nbsp\; discussed and finally concluded with discussion on Carrier Opportunities in VLSI Industry.</p>\n<p>Faculty development programme was attended by 12 &nbsp\;participants.</p>\n<p>The Event was successfully coordinated by th e <strong>Dr.Sowmya Madhavan</strong>.</p>\n<table>\n<tbody>\n<tr>\n<td wi dth="308">\n<p><strong>Dr. Parameshachari B. D.</strong></p>\n<p>IEEE SB\, Professor\, ECE\, NMIT</p>\n</td>\n<td width="308">\n<p>&nbsp\;</p>\n<p>< strong>Dr. Ramachandra A C</strong></p>\n<p>Professor and HOD</p>\n<p>Dept . of ECE\, NMIT Bengaluru</p>\n<p>&nbsp\;</p>\n</td>\n</tr>\n</tbody>\n</t able> END:VEVENT END:VCALENDAR