BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Europe/Zurich BEGIN:DAYLIGHT DTSTART:20230326T030000 TZOFFSETFROM:+0100 TZOFFSETTO:+0200 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=3 TZNAME:CEST END:DAYLIGHT BEGIN:STANDARD DTSTART:20231029T020000 TZOFFSETFROM:+0200 TZOFFSETTO:+0100 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=10 TZNAME:CET END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20230422T053824Z UID:5BDD08CC-00B0-4C08-AAB5-68ABCECCF889 DTSTART;TZID=Europe/Zurich:20230418T160000 DTEND;TZID=Europe/Zurich:20230418T173000 DESCRIPTION:Speaker:\n\nProf. Yiran Chen\, IEEE CAS Distinguished Lecturer\ n\nDuke University\, USA\n\nTitle:\n\nSoftware-Hardware Co-design of Edge AI Systems\n\nAbstract:\n\nArtificial Intelligence (AI) has become pervasi ve in cloud and edge systems alike. However\, despite the time-sensitive n ature of many edge AI tasks\, such edge systems are resource constrained\, making the deployment of many large AI models on the edge unfeasible. Cro ss-layer optimizations bridge the gap between model size and edge resource s by (1) reducing the computation and memory cost of the model and (2) imp roving the performance and efficiency of the device. In this talk\, we pre sent an overview of our effort in boosting the deployment of AI in edge sy stems. We first introduce efficient AI models via hardware-friendly model compression and topology-aware Neural Architecture Search to optimize qual ity-efficiency trade-off on AI models. Then\, we involve cross-optimized d esign of edge AI hardware using efficient dataflows\, sparse-skipping mech anisms\, and quantization. Lastly\, we demonstrate the capabilities of suc h AI models on a wide range of applications and scenarios\, such as Electr onic Design Automation (EDA) and reliable Machine Learning. Through the pr evious exploration\, we present our vision on the future challenges and op portunities of full-stack Edge AI.\n\nCo-sponsored by: Safari Research Gro up\, ETH Zurich\n\nSpeaker(s): Yiran Chen\, \n\nRoom: E12\, Bldg: ML\, Tan nenstrasse 3\, Zurich\, Switzerland\, Switzerland\, 8006\, Virtual: https: //events.vtools.ieee.org/m/357252 LOCATION:Room: E12\, Bldg: ML\, Tannenstrasse 3\, Zurich\, Switzerland\, Sw itzerland\, 8006\, Virtual: https://events.vtools.ieee.org/m/357252 ORGANIZER:shih@ini.uzh.ch SEQUENCE:14 SUMMARY:IEEE Swiss CAS Distinguished Lecture by Dr. Yiran Chen URL;VALUE=URI:https://events.vtools.ieee.org/m/357252 X-ALT-DESC:Description: <br /><h3>Speaker:</h3>\n<p dir="auto">Prof. Yiran Chen\, IEEE CAS Distinguished Lecturer</p>\n<p dir="auto">Duke University\ , USA</p>\n<h3>Title:</h3>\n<p dir="auto">Software-Hardware Co-design of E dge AI Systems</p>\n<h3>Abstract:</h3>\n<p>Artificial Intelligence (AI) ha s become pervasive in cloud and edge systems alike. However\, despite the time-sensitive nature of many edge AI tasks\, such edge systems are resour ce constrained\, making the deployment of many large AI models on the edge unfeasible. Cross-layer optimizations bridge the gap between model size a nd edge resources by (1) reducing the computation and memory cost of the m odel and (2) improving the performance and efficiency of the device. In th is talk\, we present an overview of our effort in boosting the deployment of AI in edge systems. We first introduce efficient AI models via hardware -friendly model compression and topology-aware Neural Architecture Search to optimize quality-efficiency trade-off on AI models. Then\, we involve c ross-optimized design of edge AI hardware using efficient dataflows\, spar se-skipping mechanisms\, and quantization. Lastly\, we demonstrate the cap abilities of such AI models on a wide range of applications and scenarios\ , such as Electronic Design Automation (EDA) and reliable Machine Learning . Through the previous exploration\, we present our vision on the future c hallenges and opportunities of full-stack Edge AI.</p>\n<p>&nbsp\;</p> END:VEVENT END:VCALENDAR