BEGIN:VCALENDAR
VERSION:2.0
PRODID:IEEE vTools.Events//EN
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
BEGIN:DAYLIGHT
DTSTART:20230312T030000
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3
TZNAME:PDT
END:DAYLIGHT
BEGIN:STANDARD
DTSTART:20231105T010000
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11
TZNAME:PST
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20231019T015030Z
UID:EF33019D-C5DA-464E-87BE-54D269660D80
DTSTART;TZID=America/Los_Angeles:20230501T140000
DTEND;TZID=America/Los_Angeles:20230501T163000
DESCRIPTION:CMOS scaling maintains economic relevance with 5nm SoCs already
  in high-volume production for 2.5 years and 3nm well into risk production
 . Modest feature size reduction and design/technology innovations co-optim
 ized primarily for logic scaling continue to offer compelling node-to-node
  power\, performance\, area\, and cost benefits. In this tutorial\, we sta
 rt with a brief history of transistor evolution to motivate the migration 
 from planar Dennard-era transistors to the fully depleted FinFET. We will 
 summarize the key process technology elements that have enabled the finFET
  CMOS nodes\, highlighting the resulting device technology characteristics
  and challenges impacting design. To address the growing effort required f
 or physical design closure\, we cover design strategies including density-
 friendly layout\, continuous active area layout\, and template-based analo
 g cells. We conclude with a discussion of what remains in finFET developme
 nt and a peek at transistor architectures on the horizon.\n\nSpeaker(s): A
 lvin Loke\, \n\nBldg: MacLeod Building \, MCLD 3038\, 2356 Main Mall\, Van
 couver\, British Columbia\, Canada\, V6T 1Z4
LOCATION:Bldg: MacLeod Building \, MCLD 3038\, 2356 Main Mall\, Vancouver\,
  British Columbia\, Canada\, V6T 1Z4
ORGANIZER:
SEQUENCE:3
SUMMARY:Nanoscale FinFET Technology for Circuit Designers
URL;VALUE=URI:https://events.vtools.ieee.org/m/359111
X-ALT-DESC:Description: <br /><p>CMOS scaling maintains economic relevance 
 with 5nm SoCs already in high-volume production for 2.5 years and 3nm well
  into risk production. Modest feature size reduction and design/technology
  innovations co-optimized primarily for logic scaling continue to offer co
 mpelling node-to-node power\, performance\, area\, and cost benefits. In t
 his tutorial\, we start with a brief history of transistor evolution to mo
 tivate the migration from planar Dennard-era transistors to the fully depl
 eted FinFET. We will summarize the key process technology elements that ha
 ve enabled the finFET CMOS nodes\, highlighting the resulting device techn
 ology characteristics and challenges impacting design. To address the grow
 ing effort required for physical design closure\, we cover design strategi
 es including density-friendly layout\, continuous active area layout\, and
  template-based analog cells. We conclude with a discussion of what remain
 s in finFET development and a peek at transistor architectures on the hori
 zon.</p>
END:VEVENT
END:VCALENDAR