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DTSTAMP:20230619T073346Z
UID:9ECC8D6E-7242-486E-97D0-073E621C5E0A
DTSTART;TZID=Europe/Warsaw:20230614T160000
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DESCRIPTION:Abstract: Analog-to-digital converter (ADC) and phase-locked lo
 op (PLL) integrated circuits (ICs) play critical roles for the implementat
 ions of modern communication transceivers. The next-generation wireless co
 nnectivity holds unforeseen challenges with ever increasing demands on low
  latency\, low power\, and wide bandwidth. With technology scaling\, tradi
 tional signal processing in voltage domain becomes increasingly difficult 
 when high dynamic range and high linearity are required. This talk address
 es the challenges in high-performance ADC and PLL IC designs in deep-submi
 cron technologies. We present our recent research results on the time-doma
 in quantization for low-power ADCs and the CDAC-based spur cancellation fo
 r high-performance PLLs. The proposed low power ADC and PLL technologies c
 an achieve superior power efficiency for emerging applications such as 5G\
 , automobile radar\, smart machines\, IoT and digital health.\n\nCo-sponso
 red by: Silicon Creations\n\nSpeaker(s): Fa Foster Dai\, \n\nRoom: 121\, B
 ldg: B1\, AGH University\, Krakow\, Malopolskie\, Poland\, 30-059\, Virtua
 l: https://events.vtools.ieee.org/m/359720
LOCATION:Room: 121\, Bldg: B1\, AGH University\, Krakow\, Malopolskie\, Pol
 and\, 30-059\, Virtual: https://events.vtools.ieee.org/m/359720
ORGANIZER:krzysztof.kasinski@siliconcr.com
SEQUENCE:6
SUMMARY:Foster Dai - Advances in Analog-to-Digital Converters and Phase-Loc
 ked Loops
URL;VALUE=URI:https://events.vtools.ieee.org/m/359720
X-ALT-DESC:Description: <br /><p class="Default" style="text-align: justify
 \; text-justify: inter-ideograph\; text-indent: 18.0pt\;"><strong><u><span
  lang="EN-US">Abstract:</span></u></strong><span lang="EN-US"> Analog-to-d
 igital converter (ADC) and phase-locked loop (PLL) integrated circuits (IC
 s) play critical roles for the implementations of modern communication tra
 nsceivers. The next-generation wireless connectivity holds unforeseen chal
 lenges with ever increasing demands on low latency\, low power\, and wide 
 bandwidth. With technology scaling\, traditional signal processing in volt
 age domain becomes increasingly difficult when high dynamic range and high
  linearity are required. This talk addresses the challenges in high-perfor
 mance ADC and PLL IC designs in deep-submicron technologies. We present ou
 r recent research results on the time-domain quantization for low-power AD
 Cs and the CDAC-based spur cancellation for high-performance PLLs. The pro
 posed low power ADC and PLL technologies can achieve superior power effici
 ency for emerging applications such as 5G\, automobile radar\, smart machi
 nes\, IoT and digital health.</span></p>
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