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DTSTAMP:20230619T073301Z
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DTSTART;TZID=Europe/Warsaw:20230615T170000
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DESCRIPTION:Abstract: The public’s appetite for data is creating enormous
  demand for high-speed connectivity. But as data rates increase\, timing m
 argins decrease. Specifically\, as data rates double\, the timing margin\,
  or jitter\, allocated to a system must cut in half. At the heart of timin
 g\, reference clocks (refclks) are used to time data in a communications c
 hannel. As such\, the refclk consumes a portion of the overall system jitt
 er budget. This talk discusses the evolution of refclk jitter from a stand
 ards perspective\, focusing on the latest developments in PCI Express and 
 its implication for the timing and SerDes industries in general. We explai
 n the need to move from oscilloscope to phase-noise analyzer measurements 
 of refclk jitter\, how to technically account for their differences\, and 
 propose a methodology\, or template\, for SerDes vendors to specify refclk
  jitter in their datasheets. Widespread adoption of this methodology enabl
 es SerDes vendors and their customers to optimize link performance while s
 implifying refclk selection.\n\nCo-sponsored by: Silicon Creations\n\nSpea
 ker(s): Gary Giust\, \n\nRoom: 121\, Bldg: B-1\, AGH University\, Kraków\
 , Malopolskie\, Poland\, 30-059\, Virtual: https://events.vtools.ieee.org/
 m/360364
LOCATION:Room: 121\, Bldg: B-1\, AGH University\, Kraków\, Malopolskie\, P
 oland\, 30-059\, Virtual: https://events.vtools.ieee.org/m/360364
ORGANIZER:krzysztof.kasinski@siliconcr.com
SEQUENCE:17
SUMMARY:Gary Giust - How to specify refclk jitter for SerDes applications
URL;VALUE=URI:https://events.vtools.ieee.org/m/360364
X-ALT-DESC:Description: <br /><p><strong>Abstract</strong>: The public&rsqu
 o\;s appetite for data is creating enormous demand for high-speed connecti
 vity. But as data rates increase\, timing margins decrease. Specifically\,
  as data rates double\, the timing margin\, or jitter\, allocated to a sys
 tem must cut in half. At the heart of timing\, reference clocks (refclks) 
 are used to time data in a communications channel. As such\, the refclk co
 nsumes a portion of the overall system jitter budget. This talk discusses 
 the evolution of refclk jitter from a standards perspective\, focusing on 
 the latest developments in PCI Express and its implication for the timing 
 and SerDes industries in general. We explain the need to move from oscillo
 scope to phase-noise analyzer measurements of refclk jitter\, how to techn
 ically account for their differences\, and propose a methodology\, or temp
 late\, for SerDes vendors to specify refclk jitter in their datasheets. Wi
 despread adoption of this methodology enables SerDes vendors and their cus
 tomers to optimize link performance while simplifying refclk selection.</p
 >
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